ZL50020 Datasheet, PDF (1/83 Pages) Zarlink Semiconductor Inc – Enhanced 2 K Digital Switch

ZL50020
Enhanced 2 K Digital Switch
Data Sheet
Features
• 2048 channel x 2048 channel non-blocking digital
Time Division Multiplex (TDM) switch at
8.192 Mbps and 16.384 Mbps or using a
combination of ports running at 2.048, 4.096,
8.192 and 16.384 Mbps
• 32 serial TDM input, 32 serial TDM output
streams
• Output streams can be configured as bi-
directional for connection to backplanes
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
• Per-stream input and output data rate conversion
selection at 2.048, 4.096, 8.192 or 16.384 Mbps.
Input and output data rates can differ
• Per-stream high impedance control outputs
(STOHZ) for 16 output streams
• Per-stream input bit delay with flexible sampling
point selection
• Per-stream output bit and fractional bit
advancement
November 2006
Ordering Information
ZL50020GAC 256 Ball PBGA Trays
ZL50020QCC 256 Lead LQFP Trays
ZL50020QCG1 256 Lead LQFP* Trays, Bake &
Drypack
ZL50020GAG2 256 Ball PBGA** Trays, Bake &
Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
• Four frame pulse and four reference clock outputs
• Three programmable delayed frame pulse outputs
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses:61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay
for frame integrity and low latency applications
• Per Stream (32) Bit Error Rate Test circuits
complying to ITU-O.151
V_{DD_CORE}
V_{DD_IO}
V_{DD_COREA} V_{DD_IOA}
V_SS
RESET
ODE
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
S/P Converter
Input Timing
Data Memory
Connection Memory
P/S Converter
Output HiZ
Control
Output Timing
STio[31:0]
STOHZ[15:0]
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Internal Registers &
Microprocessor Interface
Test Port
Figure 1 - ZL50020 Functional Block Diagram
1
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Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.