ZL49010_07 Datasheet, PDF (1/15 Pages) Zarlink Semiconductor Inc – Wide Dynamic Range DTMF Receiver

ZL49010/11, ZL49020/21, ZL49030/31
Wide Dynamic Range DTMF Receiver
Data Sheet
Features
• Wide dynamic range (50 dB) DTMF Receiver
• Call progress (CP) detection via cadence
indication
• 4-bit synchronous serial data output
• Software controlled guard time for ZL490x0
• Internal guard time circuitry for ZL490x1
• Powerdown option (ZL4901x & ZL4903x)
• 3.579 MHz crystal or ceramic resonator (ZL4903x
and ZL4902x)
• External clock input (ZL4901x)
• Guarantees non-detection of spurious tones
Applications
• Integrated telephone answering machine
• End-to-end signalling
• Fax Machines
Description
The ZL490xx is a family of high performance DTMF
receivers which decode all 16 tone pairs into a 4-bit
binary code. These devices incorporate an AGC for
wide dynamic range and are suitable for end-to-end
signalling. The ZL490x0 provides an early steering
(ESt) logic output to indicate the detection of a DTMF
February 2007
Ordering Information
ZL49010/11DAA 8 Pin PDIP Tubes
ZL49020/21DAA 8 Pin PDIP Tubes
ZL49030/31DCA 18 Pin SOIC Tubes
ZL49030/31DCB 18 Pin SOIC Tape & Reel
ZL49030/31DDA 20 Pin SSOP Tubes
ZL49030/31DDB 20 Pin SSOP Tape & Reel
ZL49010/11DAA1 8 Pin PDIP* Tubes
ZL49020/21DAA1 8 Pin PDIP* Tubes
ZL49030/31DCE1 18 Pin SOIC* Tubes, Bake & Drypack
ZL49030/31DCF1 18 Pin SOIC* Tape & Reel,
Bake & Drypack
ZL49030/31DDE1 20 Pin SSOP* Tubes, Bake & Drypack
ZL49030/31DDF1 20 Pin SSOP* Tubes, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
signal and requires external software guard time to
validate the DTMF digit. The ZL490x1, with preset
internal guard times, uses a delay steering (DStD)
logic output to indicate the detection of a valid DTMF
digit. The 4-bit DTMF binary digit can be clocked out
synchronously at the serial data (SD) output. The SD
pin is multiplexed with call progress detector output. In
the presence of supervisory tones, the call progress
detector circuit indicates the cadence (i.e., envelope)
of the tone burst. The cadence information can then be
processed by an external microcontroller to identify
1
PWDN
VDD
VSS
Voltage
Bias Circuit
AGC
Anti-
alias
Filter
Dial
Tone
Filter
2
OSC2
OSC1
(CLK)
Oscillator
and
Clock
Circuit
To All Chip Clocks
1. ZL49010/1 and ZL49030/1 only.
2. ZL49020/1 and ZL49030/1 only.
3. ZL490x1 only.
High
Group
Filter
Low
Group
Filter
Steering
Circuit
Digital
Detector
Algorithm
Code
Converter
and
Latch
Energy
Detection
Figure 1 - Functional Block Diagram
Digital
Guard
Time³
Parallel to
Serial
Converter
& Latch
Mux
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2007, Zarlink Semiconductor Inc. All Rights Reserved.
ESt
or
DStD
ACK
SD