ZL38005 Datasheet, PDF (1/8 Pages) Zarlink Semiconductor Inc – Enhanced Voice Processor with Dual Wideband Codecs

ZL38005
Enhanced Voice Processor
with Dual Wideband Codecs
Data Sheet
Features
• 100 MHz (200 MIPs) Zarlink voice processor with
hardware accelerator.
• Dual narrow band (8 KHz) ∆Σ ADCs with input
buffer gain selection
• Dual narrow band (8 KHz) ∆Σ DACs
• Dual function Inter-IC Sound (I²S) port
• PCM port supports TDM (ST BUS, GCI or McBSP
framing) or SSI modes at bit rates of 128, 256, 512,
1024, 2048, 4096, 8192 or 16384 Kb/sec
• Separate slave (microcontroller) and master
(Flash) SPI ports, maximum clock rate = 25 MHz
• 11 General Purpose Input/Output (GPIO) pins
• General purpose UART port
• Bootloadable for future Zarlink software upgrades
• External oscillator or crystal/ceramic resonator
• 1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
• IEEE-1149.1 compatible JTAG port
September 2007
Ordering Information
ZL38005QCG1
ZL38005GGG2
100 Pin LQFP*
96 Pin CABGA*
Trays, Bake &
Drypack
Trays, Bake &
Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Hands-free car kits
• Full duplex speaker-phone for digital telephone
• Echo cancellation for video conferences
• Intercom Systems
• Security Systems
Buffer
Driver
Buffer
Driver
CODEC[0]
ADC
DAC
CODEC[1]
ADC
DAC
PCM P0
IRQ
I²S
Interrupt
Controller
DSP
Core
Instruction
Memory
ROM
RAM
Hardware
Accelerator
Data RAM
APLL
PCM P0
Clock
Timing
Generator
OSC
JTAG
OSCo
OSCi
PCM_CLKi
PCM_LBCi
Master
SPI
Slave
SPI
UART
GPIO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006-2007, Zarlink Semiconductor Inc. All Rights Reserved.