ZL38002_07 Datasheet, PDF (1/51 Pages) Zarlink Semiconductor Inc – Digital Echo Canceller for Hands Free Communication

ZL38002
Digital Echo Canceller for Hands Free
Communication
Data Sheet
Features
• 112 ms acoustic echo canceller
• Up to 12 dB of noise reduction
• Works with low cost voice codec. ITU-T G.711 or
signed mag µ/A-Law, or linear 2’s compliment
• Each port may operate independently in
companded format or linear format
• Advanced NLP design - full duplex speech with
no switched loss on audio paths
• Fast re-convergence time: tracks changing echo
environment quickly
• Adaptation algorithm converges even during
Double-Talk
• Designed for exceptional performance in high
background noise environments
• Provides protection against narrow-band signal
divergence
• Howling prevention stops uncontrolled oscillation
in high loop gain conditions
• Programmable offset nulling of all PCM channels
• Serial micro-controller interface
• Idle channel noise suppression
• ST-BUS, GCI, or variable-rate SSI PCM
interfaces
January 2007
Ordering Information
ZL38002QDG
ZL38002QDG1
ZL38002DGE1
ZL38002DGF1
48 Pin TQFP
48 Pin TQFP*
36 Pin QSOP*
36 Pin QSOP*
Trays
Trays
Tubes, Bake & Drypack
Tape & Reel,
Bake & Drypack
*Pb Free Matte Tin
-40°C to 85°C
• User gain control provided for speaker path
(-24 dB to +21 dB in 3 dB steps)
• Adjustable gain pads from -24 dB to +21 dB at
Xin, Sin and Sout to compensate for different
system requirements
• AGC on speaker path
• Handles up to -6 dB acoustic echo return loss
(with the appropriate gain pad settings)
• Transparent data transfer and mute options
• 20 MHz master clock operation
• Low power mode during PCM Bypass
• Bootloadable for future factory software upgrades
• 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Sin
MD1
MD2
Rout
µ/A-Law/
Linear
HP
Filter
NBSD
Gain ^{S1 +} ₊ ^S2 ADV
Pad
NLP
-
Noise
Reduction
Adaptive
Filter
Gain
Pad
R₁
CONTROL
UNIT
Double
Talk
Detector
R₁
Gain
Pad
Limiter
Linear/
µ/A-Law
Program
RAM
Program
ROM
Micro
Interface
NBSD
Howling
Controller
Linear/
µ/A-Law
-24 -> +21dB
AGC
User
Gain
Limiter
HP
Filter
µ/A-Law/
Linear
VDD
VSS
RESET FORMAT ENA2
ENA1 LAW F0i BCLK/C4i MCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved.
Sout
DATA1
DATA2
SCLK
CS
Rin