ZL30414 Datasheet, PDF (1/24 Pages) Zarlink Semiconductor Inc – SONET/SDH Clock Multiplier PLL

ZL30414
SONET/SDH Clock Multiplier PLL
Features
• Meets jitter requirements of Telcordia GR-253-
CORE for OC-192, OC-48, OC-12, and OC-3
rates
• Meets jitter requirements of ITU-T G.813 for STM-
64, STM-16, STM-4 and STM-1 rates
• Provides four LVPECL differential output clocks at
622.08 MHz
• Provides a CML differential clock at 155.52 MHz
• Provides a single-ended CMOS clock at 19.44
MHz
• Lock Indicator
• Provides enable/disable control of output clocks
• Accepts a CMOS reference at 19.44 MHz
• 3.3 V supply
Applications
• SONET/SDH line cards
• Network Element timing cards
Data Sheet
February 2005
Ordering Information
ZL30414QGC 64 Pin TQFP Trays
ZL30414QGC1 64 Pin TQFP* Trays
*Pb Free Matte Tin
-40°C to +85°C
Description
The ZL30414 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30414 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-
3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and
STM-1 rates.
The ZL30414 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 622.08 MHz, a CML differential
clock at 155.52 MHz and a single-ended CMOS
clock at 19.44 MHz. The output clocks can be
individually enabled or disabled. The ZL30414
provides a LOCK indication.
C622oEN-A
C622oEN-B
LPF
C622oEN-C
C622oEN-D
C19i
Frequency
& Phase
Detector
Loop
Filter
State
Machine
Reference
and
Bias Circuit
VCO
19.44MHz
Frequency
Dividers
and
Clock
Drivers
C622oP/N-A
C622oP/N-B
C622oP/N-C
C622oP/N-D
C155oP/N
C19o
LOCK
BIAS
VDD GND VCC
C155oEN
C19oEN
05
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.