ZL30407_06 Datasheet, PDF (1/57 Pages) Zarlink Semiconductor Inc – SONET/SDH Network Element PLL

ZL30407
SONET/SDH Network Element PLL
Data Sheet
Features
• Meets requirements of GR-253 for SONET
Stratum 3 and SONET Minimum Clocks (SMC)
• Meets requirements of GR-1244 for Stratum 3
• Meets requirements of G.813 Option 1 and 2 for
SDH Equipment Clocks (SEC)
• Generates clocks for ST-BUS, DS1, DS2, DS3,
OC-3, E1, E3, STM-1 and 19.44 MHz
• Holdover accuracy of 4x10 ^-12 meets GR-1244
Stratum 3E and ITU-T G.812 requirements
• Continuously monitors both references for
frequency accuracy exceeding ±12 ppm
• Provides “hit-less” reference switching
• Compensates for Master Clock Oscillator
accuracy
• Automatically detects frequency of both reference
clocks and synchronizes to any combination of
8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz
reference frequencies
• Allows Hardware or Microprocessor control
• Pin compatible with ZL30410, ZL30402 and
MT90401
November 2006
Ordering Information
ZL30407QCC 80 Pin LQFP Trays
ZL30407QCG1 80 Pin LQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Synchronization for SDH and SONET Network
Elements
• Clock generation for ST-BUS and GCI backplanes
Description
The ZL30407 is a Network Element Phase-Locked
Loop designed to synchronize SDH and SONET
systems. In addition, it generates multiple clocks for
legacy PDH equipment and provides timing for ST-
BUS and GCI backplanes.
VDD GND
C20i
FCS
OE
PRI
PRIOR
SEC
SECOR
RefSel
HW
RESET
Primary
Acquisition
PLL
Secondary
Acquisition
PLL
Master Clock
Frequency
Calibration
MUX
Microport
Core PLL
APLL
Clock
Synthesizer
Control State Machine
JTAG
IEEE
1149.1a
CS DS R/W A0-A6 D0-D7
MS1 MS2 RefAlign LOCK HOLDOVER
C155P/N
C34/C44
C19o
C16o
C8o
C6o
C4o
C2o
C1.5o
F16o
F8o
F0o
E3DS3/OC3
E3/DS3
Tclk
Tdi
Tdo
Tms
Trst
R1-17
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.