ZL30131 Datasheet, PDF (1/11 Pages) Zarlink Semiconductor Inc – OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer

Features
• Synchronizes to standard telecom or Ethernet
backplane clocks and provides jitter filtered output
clocks for SONET/SDH, PDH and Ethernet network
interface cards
• Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
• Two independent DPLLs provides timing for the
transmit path (backplane to line rate) and the
receive path (recovered line rate to backplane)
• Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
• Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,
or 0.1 Hz
• Supports automatic hitless reference switching and
short term holdover during loss of reference inputs
• Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g. 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Ethernet PHYs
• Programmable output synthesizers (P0, P1)
generate telecom clock frequencies from any
ZL30131
OC-192/STM-64 SONET/SDH/10GbE
Network Interface Synchronizer
Short Form Data Sheet
February 2008
Ordering Information
ZL30131GGG 100 Pin CABGA
ZL30131GGG2 100 Pin CABGA*
*Pb Free Tin/Silver/Copper
-40^oC to +85^oC
Trays
Trays
multiple of 8 kHz up to 100 MHz (e.g., T1/E1,
DS3/E3)
• Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
• Configurable input to output delay and output to
output phase alignment
• Configurable through a serial interface (SPI or I²C)
• DPLLs can be configured to provide synchronous
or asynchronous clock outputs
Applications
• ITU-T G.8262 Line Cards which support 1GbE and
10GbE interfaces
• SONET line cards up to OC-192
• SDH line cards up to STM-64
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
p1_clk0
p1_clk1
/N1
/N2
Tx
Rx
Input
Ports
Ref Mon
P1
ref_out
Tx
DPLL
osci
osco
APLL
P0
diff0_p/n
diff1_p/n
apll_clk0
apll_clk1
p0_clk0
p0_clk1
p0_fp0
p0_fp1
ref0
Rx
DPLL
ref7
mode hold lock
I²C/SPI
JTAG
Figure 1 - Functional Block Diagram
1
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