ZL30123 Datasheet, PDF (1/27 Pages) Zarlink Semiconductor Inc – Low Jitter Line Card Synchronizer

ZL30123
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
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Features
• Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
• Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
• Programmable output synthesizers (P0, P1)
generate clock frequencies from any multiple of
8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides two DPLLs which are independently
configurable through a serial peripheral interface
• DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover), and
selectable loop bandwidth
Ordering Information
May 2006
ZL30123GGG 100 Pin CABGA Trays
ZL30123GGG2 100 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40^oC to +85^oC
• DPLL2 provides a comprehensive set of features
for generating derived output clocks and other
general purpose clocks
• Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Provides 3 sync inputs for output frame pulse
alignment
• Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
• Configurable input to output delay, and output to
output phase alignment
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan
osco
osci
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
int_b
trst_b tck tdi tms tdo dpll2_ref dpll1_hs_en dpll1_lock dpll1_holdover diff0_en diff1_en
Master
Clock
IEEE 1449.1
JTAG
ref7:0
sync2:0
Reference ^{ref_&_sync_status}
Monitors
DPLL2
ref
ref
DPLL1
sync
fb_clk/fp
P0
Synthesizer
P1
Synthesizer
SONET/SDH
APLL
Feedback
Synthesizer
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
diff0
diff1
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
fb_clk
SPI Interface
Controller &
State Machine
sck
si so cs_b
rst_b
dpll1_mod_sel1:0
sdh_filter filter_ref0 filter_ref1
Figure 1 - Block Diagram
1
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Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.