ZL30111 Datasheet, PDF (1/20 Pages) Zarlink Semiconductor Inc – POTS Line Card PLL

ZL30111
POTS Line Card PLL
Data Sheet
Features
January 2007
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
19.44 MHz input
• Provides a range of clock outputs: 2.048 MHz,
4.096 MHz and 8.192 MHz
• Provides 2 styles of 8 kHz framing pulses
• Automatic entry and exit from freerun mode on
reference fail
Ordering Information
ZL30111QDG
ZL30111QDG1
64 Pin TQFP Trays, Bake & Drypack
64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Provides DPLL lock and reference fail indication
• Synchronizer for POTS line cards
• DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
• Rate convert NTR 8kHz or GPON physical
interface clock to TDM clock
• Less than 0.6 ns_pp intrinsic jitter on all output clocks _Description
• 20 MHz external master clock source: clock
oscillator or crystal
The ZL30111 POTS line card PLL contains a digital
• Simple hardware control interface
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30111 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
REF_FAIL
LOCK
Reference
Monitor
State Machine
Master
Clock
Mode
Control
DPLL
C2o
C4
C8
F4
F8
Figure 1 - Functional Block Diagram
1
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Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.