ZL30108_06 Datasheet, PDF (1/28 Pages) Zarlink Semiconductor Inc – SONET/SDH Network Interface DPLL

Features
• Supports output wander and jitter generation
specifications for GR-253-CORE OC-3 and G.813
STM-1 SONET/SDH interfaces
• Accepts two input references and synchronizes to
any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a 19.44 MHz (SONET/SDH) clock output
• Provides an 8 kHz framing pulse and a 2 kHz
multi-frame pulse
• Provides automatic entry into Holdover and return
from Holdover
• Hitless reference switching between any
combination of valid input reference frequencies
• Provides lock and accurate reference fail
indication
• Loop filter bandwidth of 29 Hz or 14 Hz
• Less than 24 ps_rms intrinsic jitter on the 19.44 MHz
output clock, compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications
• Less than 0.5 ns_pp intrinsic jitter on output frame
pulses
• External master clock source: clock oscillator or
crystal
• Simple hardware control interface
ZL30108
SONET/SDH
Network Interface DPLL
Data Sheet
March 2006
Ordering Information
ZL30108LDA
ZL30108LDE1
32 Pin QFN Tubes
32 Pin QFN* Tubes, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Line card synchronization for SONET/SDH
systems
Description
The ZL30108 SONET/SDH network interface digital
phase-locked loop (DPLL) provides timing and
synchronization for SONET/SDH network interface
cards.
The ZL30108 generates a SONET/SDH clock and
framing signals that are phase locked to one of two
backplane or network references. It helps ensure
system reliability by monitoring its references for
frequency accuracy and stability and by maintaining
tight phase alignment between the input reference
clock and clock outputs.
The ZL30108 output clock’s wander and jitter
generation are compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications.
OSCi OSCo TIE_CLR
LOCK
REF0
REF1
REF_FAIL0
REF_FAIL1
OOR_SEL
REF_SEL
RST
MODE_SEL
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
Frequency
Synthesizer
C19o
F8ko
F2ko
Figure 1 - Functional Block Diagram
1
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