ZL30106 Datasheet, PDF (1/48 Pages) Zarlink Semiconductor Inc – SONET/SDH/PDH Network Interface DPLL

ZL30106
SONET/SDH/PDH
Network Interface DPLL
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between inputs and outputs
• Supports output wander and jitter generation
specifications for SONET/SDH and PDH
interfaces
• Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs:
- 2.048 MHz (E1), 16.384 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
- 19.44 MHz (SONET/SDH)
- 1.544 MHz (DS1) and 3.088 MHz
- a choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Provides automatic entry into Holdover and return
from Holdover
• Manual and automatic hitless reference switching
• Provides lock, holdover and accurate reference
fail indication
October 2004
Ordering Information
ZL30106QDG 64 pin TQFP
-40°C to +85°C
• Selectable loop filter bandwidth of 29 Hz or
922 Hz
• Less than 24 ps_rms intrinsic jitter on the
19.44 MHz output clock, compliant with GR-253-
CORE OC-3 and G.813 STM-1 specifications
• Less than 0.6 ns_pp intrinsic jitter on all PDH output
clocks and frame pulses
• Selectable external master clock source: clock
oscillator or crystal
• Simple hardware control interface
Applications
• Line card synchronization for SONET/SDH and
PDH systems
• Wireless base-station Network Interface Card
• AdvancedTCA™ and H.110 line cards
OSCi OSCo TIE_CLR
BW_SEL LOCK
OUT_SEL2
REF0
REF_SYNC0
REF1
REF_SYNC1
REF2
REF_FAIL0
REF_FAIL1
REF_FAIL2
APP_SEL1:0
REF_SEL1:0
RST
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
SDH
Synthesizer
Programmable
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
TRST
MODE_SEL1:0 HMS
HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.