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ZL30100_06 Datasheet, PDF (1/36 Pages) Zarlink Semiconductor Inc – T1/E1 System Synchronizer
ZL30100
T1/E1 System Synchronizer
Data Sheet
Features
February 2006
• Supports Telcordia GR-1244-CORE Stratum 4 and
Stratum 4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
Ordering Information
ZL30100QDC 64 Pin TQFP Trays
ZL30100QDG1 64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
-40°C to +85°C
• Simple hardware control interface
• Accepts two input references and synchronizes to
any combination of 8 kHz, 1.544 MHz, 2.048 MHz,
8.192 MHz or 16.384 MHz inputs
• Less than 0.6 nspp intrinsic jitter on all output
clocks
• External master clock source: clock oscillator or
crystal
• Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz and either 4.096 MHz and
8.192 MHz or 32.768 MHz and 65.536 MHz
• Hitless reference switching between any
combination of valid input reference frequencies
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1.5 x 10-7
• Lock, Holdover and selectable Out of Range
indication
Applications
• Synchronization and timing control for multi-trunk
DS1/E1 systems such as DSLAMs, gateways and
PBXs
• Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
• Line Card synchronization for PDH systems
• Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
REF0
REF1
REF_FAIL0
REF_FAIL1
OOR_SEL
REF_SEL
RST
OSCi OSCo TIE_CLR
BW_SEL LOCK OUT_SEL
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Feedback Frequency
Select
MUX
DS1
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
TRST
MODE_SEL1:0 HMS HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
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Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.