ZL10313 Datasheet, PDF (1/26 Pages) Zarlink Semiconductor Inc – Satellite Demodulator

ZL10313
Satellite Demodulator
Data Sheet
Features
• Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
• On-chip digital filtering supports 1 - 45 MSps
symbol rates
• On-chip 60 or 90 MHz dual-ADC
• High speed scanning mode for blind symbol
rate/code rate acquisition
• Automatic spectral inversion resolution
• High level software interface for minimum
development time
• Up to ±22.5 MHz LNB frequency tracking
• DiSEqC™ v2.2: receive/transmit for full control of
LNB, dish and other components
• Compact 64-pin LQFP package (7 x 7 mm)
• A full DVB-S front-end reference design is
available, ref. ZLE10538
Applications
• DVB 1 - 45 MSps compliant satellite receivers
• DSS 20 MSps compliant satellite receivers
• SMATV (Single Master Antenna TV) trans-
modulators
• Satellite PC applications
November 2004
Ordering Information
ZL10313QCG
ZL10313QCG1
ZL10313UBH
64 Pin LQFP Trays, Bake & Drypack
64 Pin LQFP* Trays, Bake & Drypack
Die supplied in wafer form**
*Pb Free Matte Tin
**Please contact Sales for further details
0°C to +70°C
Description
The ZL10313 is a QPSK/BPSK 1 - 45 MSps
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, implements the complete
DVB/DSS FEC (Forward Error Correction) and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10313 also provides automatic gain control to the RF
front-end device.
The ZL10313 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10313 because of the built in automatic
search and decode control functions.
I I/P
Q I/P
Dual ADC
De-rotator
Decimation
Filtering
Timing recovery
Matched filter
Phase recovery
DVB
DSS
FEC
MPEG/
DSS
Packets
Analog
AGC
Control
Clock Generation
Acquisition
Control
2-Wire Bus ^{Bus I/O}
Interface
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.