VP16256 Datasheet, PDF (1/19 Pages) Mitel Networks Corporation – Programmable FIR Filter

VP16256
Programmable FIR FIlter
Advance Information
The VP16256 contains sixteen multiplier - accumulators, which
can be multi cycled to provide from 16 to 128 stages of digital filtering.
Input data and coefficients are both represented by 16-bit two’s
complement numbers with coefficients converted internally to 12 bits
and the results being accumulated up to 32 bits.
In 16-tap mode the device samples data at the system clock rate
of up to 40MHz. If a lower sample rate is acceptable then the number
of stages can be increased in powers of two up to a maximum of 128.
Each time the number of stages is doubled, the sample clock rate
must be halved with respect to the system clock. With 128 stages the
sample clock is therefore one eighth of the system clock.
In all speed modes devices can be cascaded to provide filters of
any length, only limited by the possibility of accumulator overflow. The
32-bit results are passed between cascaded devices without any
intermediate scaling and subsequent loss of precision.
The device can be configured as either one long filter or two
separate filters with half the number of taps in each. Both networks
can have independent inputs and outputs.
Both single and cascaded devices can be operated in decimate-
by-two mode. The output rate is then half the input rate, but twice the
number of stages are possible at a given sample rate. A single device
with a 40MHz clock would then, for example, provide a 128-stage low
pass filter, with a 10MHz input rate and 5MHz output rate.
Coefficients are stored internally and can be down loaded from
a host system or an EPROM. The latter requires no additional
support, and is used in stand alone applications. A full set of
coefficients is then automatically loaded at power on, or at the request
of the system. A single EPROM can be used to provide coefficients
for up to 16 devices.
INPUT
DATA
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
RES
VP
16256
OUTPUT
DATA
EPROM
SCLK
GND
Fig. 1 A dual filter application
ANALOG
INPUT
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
ADC
RES
COEFFICIENTS
VP
16256
EPROM
OUTPUT
DATA
CLKOP
SCLK GND
Fig. 2 Typical system application
DS4548
ISSUE 4.0
PIN 1
August 1998
PIN 1 IDENT
PIN
208
GH208
Pin identification diagram (top view)
See Table 1 for pin descriptions and Table 2 for pinout
FEATURES
I Sixteen MACs in a Single Device
I Basic Mode is 16-Tap Filter at up to 40MHz
Sample Rates
I Programmable to give up to 128 Taps with
Sampling Rates Proportionally Reducing to 5MHz
I 16-bit Data and 32-bit Accumulators
I Can be configured as One Long Filter or Two Half-
Length Filters
I Decimate-by-two Option will Double the Filter
Length
I Coefficients supplied from a Host System or a local
EPROM
I 208-Pin Plastic PowerQuad PQ2 Package
APPLICATIONS
I High Performance Commercial Digital Filters
I Matrix Multiplication
I Correlation
I High Performance Adaptive Filtering
ORDERING INFORMATION
VP16256-27/CG/GH1N 27MHz, Commercial
PowerQuad PQ2 package (GH208)
VP16256-40/CG/GH1N 40MHz, Commercial
PowerQuad PQ2 package (GH208)
plastic
plastic