SP5730 Datasheet, PDF (1/12 Pages) Mitel Networks Corporation – 1.3GHz Low Phase Noise Frequency Synthesiser

SP5730
1.3 GHz Low Phase Noise Frequency Synthesiser
Data Sheet
Features
• Complete 1·3 GHz Single Chip System for Digital
Terrestrial Television Applications
• Selectable Reference Division Ratio, Compatible with
DTT Requirements
• Optimised for Low Phase Noise, with Comparison
Frequencies up to 4 MHz
• No RF Prescaler
• Selectable Reference/Comparison Frequency Output
• Four Selectable I²C Addresses
• I²C Fast Mode Compliant with 3·3V and 5V Logic
Levels
• Four Switching Ports
• Functional Replacement for SP5659 (except ADC)
• Pin Compatible with SP5655
• Power Consumption 120mW with V_CC = 5·5V, all Ports off
• ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
• Digital Satellite, Cable and Terrestrial Tuning Systems
• Communications Systems
Description
The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1·3GHz and is
optimised for digital terrestrial applications. The RF
preamplifier interfaces direct with the RF programmable
divider, which is of MN1A construction so giving a step
size equal to the loop comparison frequency and no
November 2004
Ordering Information
SP5730A/KG/QP1T 16 Pin QSOP Tape & Reel
SP5730A/KG/QP1S 16 Pin QSOP Tubes
SP5730A/KG/MP1S 16 Pin SOIC Tubes
SP5730A/KG/MP2S 16 Pin SOIC* Tubes
SP5730A/KG/QP2T 16 Pin QSOP* Tape & Reel
SP5730A/KG/MP1T 16 Pin SOIC Tape & Reel
SP5730A/KG/MP2T 16 Pin SOIC* Tape & Reel
SP5730A/KG/QP2S 16 Pin QSOP* Tubes
*Pb Free Matte Tin
prescaler phase noise degradation over the full RF
operating range. The comparison frequency is obtained
either from an on-chip crystal controlled oscillator, or from
an external source. The oscillator frequency, f_REF, or phase
comparator frequency, f_COMP, can be switched to the REF/
COMP output providing a reference for a second
frequency synthesiser. The synthesiser is controlled via
an 1²C bus and is fast mode compliant. It can be hard
wired to respond to one of four addresses to enable two
or more synthesisers to be used on a common bus. The
device contains four switching ports P0 - P3.
Absolute Maximum Ratings
All voltages are referred to V_EE = 0V
Supply voltage, V_CC
RF differential input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
QP16 thermal resistance
Chip to ambient, θ_JA
Chip to case, θ_JC
-0·3V to +7V
2·5Vp-p
-0·3 to V_CC +0·3V
-0·3 to 6V
-55°C to +150°C
+150°C
80°C/W
20°C/W
13
RF
INPUT ¹⁴
48/9
ADDRESS ¹⁰
SDA ⁴
SCL ⁵
I²C BUS
TRANSCEIVER
12-BIT
COUNT
3-BIT
COUNT
LOCK
fPD/2
REFERENCE
DIVIDER
ENABLE/
SELECT
PUMP
CP MODE
11 _REF/COMP
2 _{CRYSTAL CAP}
3 _CRYSTAL
1 _{CHARGE PUMP}
16 _DRIVE
DISABLE
15-BIT LATCH
2 BIT
5 BIT
2 BIT
2 BIT
4-BIT LATCH AND
PORT INTERFACE
67
89
P3 P2 P1 P0
Figure 1 - SP5730 block diagram
f_PD/2 SELECT
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