PDSP16116 Datasheet, PDF (1/18 Pages) Mitel Networks Corporation – 16 X 16 Bit Complex Multiplier

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16 by 16 Bit Complex Multiplier
The PDSP16116A will multiply two complex (16 + 16) bit
words every 50ns and can be configured to output the
complete complex (32 + 32) bit result within a single cycle. The
data format is fractional two's complement.
The PDSP16116/A contains four 16 x 16 Array Multipliers,
two 32 bit Adder/Subtractors and all the control logic required
to support Block Floating Point Arithmetic as used in FFT
applications. In combination with a PDSP16318, the
PDSP16116A forms a two chip 10MHz Complex Multiplier
Accumulator with 20 bit accumulator registers and output
shifters. The PDSP16116 in combination with two
PDSP16318s and two PDSP1601s forms a complete 10MHz
Radix 2 DIT FFT Butterfly solution which fully supports Block
Floating Point Arithmetic. The PDSP16116/A has an
extremely high throughput that is suited to recursive
algorithms as all calculations are performed with a single
pipeline delay (two cycle fall-through).
FEATURES
s Complex Number (16 + 16) X (16 + 16) Multiplication
s Full 32 bit Result
s 20MHz Clock Rate
s Block Floating Point FFT Butterfly Support
s -1 times -1 Trap
s Two's Complement Fractional Arithmetic
s TTL Compatible I/O
s Complex Conjugation
s 2 Cycle Fall Through
s 144 pin PGA or QFP packages
APPLICATION
s Fast Fourier Transforms
s Digital Filtering
s Radar and Sonar Processing
s Instrumentation
s Image Processing
ASSOCIATED PRODUCTS
PDSP16318/A
PDSP16112/A
PDSP16330/A
PDSP1601/A
PDSP16350
PDSP16256
PDSP16510
Complex Accumulator
(16 + 16) X (12 + 12) Complex Multiplier
Pythagoras Processor
ALU and Barrel Shifter
Precision Digital Modulator
Programmable FIR Filter
Single Chip FFT Processor
DS3858
ISSUE 3.0
June 2000
Ordering Information
PDSP16116 MC GC1R 10MHz MIL-883 screened -
ceramic QFP
PDSP16116 MC AC1R 10MHz MIL-883 screened -
PGA package
PDSP16116A MC GC1R 20MHz MIL-883 screened -
ceramic QFP
PDSP16116A MC AC1R20MHz MIL-883 screened -
PGA package
XR
REG
XI
REG
YR
REG
YI
REG
MULT
MULT
MULT
MULT
REG
REG
REG
REG
+/-
+/-
SHIFT
SHIFT
REG
REG
PR
PI
Fig.1 Simplified Block Diagram
CHANGE NOTIFICATION
The change notification requirements of MIL-M-38510 will be
implemented on this device type. Known customers will be
notified of any changes since last buy when ordering further
parts if significant changes have been made.
Rev
Date
A
B
C
JULY 1993 OCT 1998 JUN 2000
D
1