NJ88C24 Datasheet, PDF (1/6 Pages) Zarlink Semiconductor Inc – Frequency Synthesiser with non-resettable counters

NJ88C24
Frequency Synthesiser with non-resettable counters
DS2438 - 2.3
The NJ88C24 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable ‘M’ counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters, subsequent updating can be
abbreviated to 17 bits, when only the ‘A’ and‘M’ counters require
changing.
The NJ88C24 is intended to be used in conjunction with a
two-modulus prescaler such as the SP8710 or SP8705 series
to produce a universal binary coded synthesiser for up to
1100MHz operation.
FEATURES
s Low Power Consumption
s High Performance Sample and Hold Phase Detector
s Serial Input with Fast Update Feature
s >20MHz Input Frequency
s Fast Lock-up Time
ORDERING INFORMATION
NJ88C24 MA DG Ceramic DIL Package
NJ88C24 MA DP Plastic DIL Package
NJ88C24 MA MP Miniature Plastic DIL Package
PDA 1
16 CH
PDB 2
15 RB
LD 3
14 MC
FIN
V_SS
V_DD
OSC IN
OSC OUT
4
13
NJ88C24
5
12
6
11
7
10
8
9
PDA
CAP
PDB
ENABLE ^NC
LD
CLOCK
F_IN
V_SS
DATA
V_DD
NC
NC
OSC IN
DG16, DP16
1
18
2
17
3
16
4
15
5 NJ88C24 14
6
13
7
12
8
11
9
10
MP18
CH
RB
MC
CAP
ENABLE
CLOCK
DATA
NC
OSC OUT
Fig.1 Pin connections - top view (not to scale)
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V_DD2V_SS:
Input voltage
20·5V to 7V
Open drain output, LD pin:
7V
All other pins:
Storage temperature:
V_SS20·3V to V_DD10·3V
255°C to 1125°C
(DP and MP packages)
265°C to 1150°C
(DG package)
7 (9)
OSC IN
8 (10)
OSC OUT
10 (12)
DATA _{12 (14)}
ENABLE
11 (13)
CLOCK
REFERENCE COUNTER
(11BITS)
LATCH 6 LATCH 7 LATCH 8
‘R’ REGISTER
‘M’ REGISTER
42
f_r
RB CAP CH
15 17 16
(17) (15) (18)
SAMPLE/HOLD 1 (1)
PHASE
PDA
DETECTOR
f_V
‘A’ REGISTER
FREQUENCY/ 2 (2)
PHASE
PDB
DETECTOR
3 (4)
LOCK DETECT (LD)
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
V_SS
4 (5)
F_IN
6 (7)
V_DD
5 (6)
V_SS
‘M’ COUNTER
(10 BITS)
‘A’ COUNTER
(7 BITS)
CONTROL LOGIC
Fig.2 Block diagram
14 (16) ^MODULUS
CONTROL
OUTPUT (MC)