MT93L00A Datasheet, PDF (1/39 Pages) Zarlink Semiconductor Inc – Multi-Channel Voice Echo Canceller

MT93L00A
Multi-Channel Voice Echo Canceller
Data Sheet
Not recommended for new designs. Use the
ZL38065, 32 channel VEC with enhanced
algorithm.
Features
• Independent multiple channels of echo
cancellation; from 32 channels of 64 ms to 16
channels of 128 ms with the ability to mix
channels at 128 ms or 64 ms in any combination
• Independent Power Down mode for each group of
2 channels for power management
• ITU-T G.165 and G.168 compliant
• Field proven, high quality performance
• Compatible to ST-BUS and GCI interface at
2 Mbps serial PCM
• PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
• Per channel Fax/Modem G.164 2100 Hz or G.165
2100 Hz phase reversal Tone Disable
• Per channel echo canceller parameters control
• Transparent data transfer and mute
• Fast reconvergence on echo path changes
• Non-Linear Processor with high quality subjective
performance
March 2005
Ordering Information
MT93L00AB 100-Pin LQFP
MT93L00AV 208-Ball LBGA
-40°C to +85°C
• Protection against narrow band signal divergence
• Offset nulling of all PCM channels
• 10 MHz or 20 MHz master clock operation
• 3.3 V pads and 1.8 V Logic core operation with
5 V tolerant inputs
• No external memory required
• Non-multiplexed microprocessor interface
• IEEE-1149.1 (JTAG) Test Access Port
• Applications
• Voice over IP network gateways
• Voice over ATM, Frame Relay
• T1/E1/J1 multichannel echo cancellation
• Wireless base stations
• Echo Canceller pools
• DCME, satellite and multiplexer systems
Rin
Sin
MCLK
Fsel
C4i
F0i
V_{DD1 (3.3 V)}
V_SS
V_{DD2 (1.8 V)}
ODE
Serial
to
Parallel
PLL
Timing
Unit
Echo Canceller Pool
Group 0 Group 1 Group 2 Group 3
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Group 4 Group 5 Group 6 Group 7
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Group 8 Group 9 Group 10 Group 11
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Group 12 Group 13 Group 14 Group 15
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Parallel
to
Serial
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Microprocessor Interface
Test Port
Rout
Sout
IC0
RESET
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram
1
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Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.