MT9171 Datasheet, PDF (1/25 Pages) Mitel Networks Corporation – ISO2-CMOS ST-BUS™ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

ISO²-CMOS ST-BUS FAMILY MT9171/72
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Features
• Full duplex transmission over a single twisted
pair
• Selectable 80 or 160 kbit/s line rate
• Adaptive echo cancellation
• Up to 3km (9171) and 4 km (9172)
• ISDN compatible (2B+D) data format
• Transparent modem capability
• Frame synchronization and clock extraction
• Zarlink ST-BUS compatible
• Low power (typically 50 mW), single 5V supply
Applications
• Digital subscriber lines
• High speed data transmission over twisted
wires
• Digital PABX line cards and telephone sets
• 80 or 160 kbit/s single chip modem
DS5130
ISSUE 3
February 1999
Ordering Information
MT9171AE 22 Pin Plastic DIP (400 mil)
MT9171AN 24 Pin SSOP
MT9171AP 28 Pin PLCC
MT9172AE 22 Pin Plastic DIP (400 mil)
MT9172AN 24 Pin SSOP
MT9172AP 28 Pin PLCC
-40°C to +85°C
Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for
pin compatible replacements for the MT8971 and
MT8972, respectively. They are multi-function
devices capable of providing high speed, full duplex
digital transmission up to 160 kbit/s over a twisted
wire pair. They use adaptive echo-cancelling
techniques and transfer data in (2B+D) format
compatible to the ISDN basic rate. Several modes of
operation allow an easy interface to digital
telecommunication networks including use as a high
speed limited distance modem with data rates up to
160 kbit/s. Both devices function identically but with
the DSIC having a shorter maximum loop reach
specification. The generic "DNIC" will be used to
reference both devices unless otherwise noted.
The MT9171/72 is fabricated in Zarlink’s ISO²-
CMOS process.
DSTi/Di
CDSTi/
CDi
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
DSTo/Do
CDSTo/
CDo
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
Control Transmit
Register Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control _{Sync Detect}
DPLL
Status
Receive
Address
Echo Canceller
Error
Signal Echo Estimate
—
+
∑
Receive
Filter
V_Bias
MUX
-1
+2
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
V_DD V_SS V_Bias V_Ref
Figure 1 - Functional Block Diagram
L_OUT
L_OUT
DIS
Precan
L_IN
OSC2
OSC1
9-115