MT8888C Datasheet, PDF (1/25 Pages) Mitel Networks Corporation – Integrated DTMFTransceiver with Intel Micro Interface

MT8888C
Integrated DTMF Transceiver
with Intel Micro Interface
Data Sheet
Features
• Central office quality DTMF transmitter/receiver
• Low power consumption
• High speed Intel micro interface
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30 dBm
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers
Description
The MT8888C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
September 2005
Ordering Information
MT8888CE
MT8888CS
MT8888CN
MT8888CP
MT8888CE1
MT8888CS1
MT8888CN1
MT8888CP1
MT8888CPR
MT8888CSR
MT8888CSR1
MT8888CPR1
20 Pin PDIP
20 Pin SOIC
24 Pin SSOP
28 Pin PLCC
20 Pin PDIP*
20 Pin SOIC*
24 Pin SSOP*
28 Pin PLCC*
28 Pin PLCC
20 Pin SOIC
20 Pin SOIC*
28 Pin PLCC*
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8888C utilizes an Intel micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
TONE
∑
D/A
Converters
IN+
IN-
GS
OSC1
OSC2
Tone Burst
Gating Cct.
+
Dial
-
Tone
Filter
Oscillator
Circuit
Bias
Circuit
Control
Logic
High Group
Filter
Low Group
Filter
Control
Logic
Row and
Column
Counters
Digital
Algorithm
and Code
Converter
Steering
Logic
Transmit Data
Register
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Data
Bus
Buffer
Interrupt
Logic
I/O
Control
V_DD V_Ref V_SS
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
D0
D1
D2
D3
IRQ/CP
RD
CS
WR
RS0