ISL40 Datasheet, PDF (7/12 Pages) Yamar Electronics Ltd. – Independent DC-LIN Slave For Asynchronous Communication Over Noisy Lines

Proprietary and Confidential Information of YAMAR Electronics Ltd.
4 ISL40 SIGNALS
Device signals are defined in table 4.1.
Table 4.1 - Device signals
Control signals
Configuration signals
HDO
nSleep
INH
Wake
nReset
InterfHop
Interfer
Front-end signals
CMOS
O
CMOS
I
CMOS
I
CMOS
I
CMOS_Reset+PU I
CMOS + PD
I
CMOS
O
20 F0F1-0
28 F0F1-1
24 F0F1-2
33 F0F1-3
32 BitRate0
36 BitRate1
21 Mode3 =1
Mode4 =1
CMOS+PD I 42
CMOS+PD I
43
CMOS+PD I
34
CMOS+PD I
35
CMOS+PD I
45
CMOS+PD I
46
CMOS+PD I
4
CMOS+PD I
7
RxOn
DRxP
DRxN
MF0nF1
TxOn
DTxO
OscIn
OscOut
CMOS
O
CMOS
I
CMOS
I
CMOS
O
CMOS
O
Buf+Slew+3 State B
CMOS
I
CMOS
O
16 nExtendIn
6 AutoFreqCh
AutoSleep
5 Power signals
41 Vcc
14 Vcc
13 Gnd
1 Gnd
2 VccPLL
GndPLL
CMOS+PD I
40
CMOS+PD I
26
CMOS+PD I
27
Power
Power
Power
Power
Power
Power
P
48
P
3
P
12
P
19
P
37
P
47
Sig I/O signals
SigIn0
CMOS+PD
I
38
SigIn1
SigIn2
SigIn3
SigIO4
SigIO5
SigIO6
SigIO7
SigO0
SigO1
SigO2
SigO3
ID0
ID1
ID2
ID3
CMOS+PD
I
39
CMOS
I
25
CMOS
I
29
BiDirectional+PD B
23
BiDirectional+PD B
15
BiDirectional+PD B
17
BiDirectional+PD B
18
CMOS
O
8
CMOS
O
9
CMOS
O 10
CMOS
O 11
CMOS+PD
I
30
CMOS+PD
I
31
CMOS+PD
I
44
CMOS+PD
I
22
PD = internal pull down resistor
1
2
3
4
5
6
7
8
9
10
11
12
OscOut
OscIn
Vcc
Mode3
DRxN
DRxP
Mode4
SigO0
SigO1
SigO2
SigO3
Gnd
ISL40
Interf Hop
F0F1-3
F0F1-2
Wake
nReset
Id1
Id0
SigIn3
nSleep
AutoSleep
AutoFreqChange
SigIn2
36
35
34
33
32
31
30
29
28
27
26
25
Figure 4.1 - ISL40 Pinout
© 2007 Yamar Electronics Ltd.
7
DS-ISL40 R1.6