YDA131 Datasheet, PDF (4/18 Pages) YAMAHA CORPORATION – D- 1 STEREO 2.5W DIGITAL AUDIO POWER AMPLIFIER

YDA131
■Description of terminal functions
VDDPL, VSSPL, VDDPR, VSSPR (Pin No.22, 20&23, 15, 14&17)
These are the power supply and ground terminals for the output buffers.
VDDPL and VSSPL are the power supply and ground terminals for the left channel, and VDDPR and VSSPR are the power
supply and ground terminals for the right channel.
There are two VSSPL terminals and two VSSPR terminals, both of which are to be connected with similar impedance
(length of patterns on the printed circuit board).
OUTPL, OUTML, OUTPR, OUTMR (Pin No.19, 21, 18, 16) [Digital-OUT]
These are the output buffer terminals and output digital pulse signal that has been modulated by PWM system.
OUTPL and OUTML are the output buffer terminals for the left channel, OUTPL is the positive terminal and OUTML is
the negative terminal.
OUTPR and OUTMR are the output buffer terminals for the right channel, OUTPR is the positive terminal and OUTMR is
the negative terminal.
Since both channels are BTL (Bridge-Tied Load) output, the minus terminal is not at the ground potential.
Connect the IC with the speakers through an LC filter as shown in the "Application circuit" for the purpose of removing the
carrier frequency signal.
VDDL, VSSL, VDDR, VSSR (Pin No.5, 4, 8, 9)
These are the power supply and ground terminals for the circuitries other than the output buffers.
VDDL and VSSL are the power supply and ground terminals for the left channel circuit.
VDDR and VSSR are the power supply and ground terminals for the right channel circuit.
VSS (Pin No.6)
This is the ground terminal for the protection circuitry and the control circuitry.
Connect VSS to the left-channel analog ground near the terminal.
INL, VPL, INR, VPR (Pin No.2, 1, 11, 12) [Analog]
These are the audio signal input and gain adjustment terminals.
INL and VPL are the audio signal input and gain adjustment terminals for the left channel.
INR and VPR are the audio signal input and gain adjustment terminals for the right channel.
The terminals are connected respectively to the inversion input and output of the first stage inversion operational amplifiers.
The amplifier gain is set by connecting an input resistor and a feedback resistor to both terminals as shown the "Application
circuit". The use of this inversion operational amplifier allows making a simple filter.
For the details, refer to "Gain setting" on page 6.
VREFL, VREFR (Pin No.3, 10) [Analog]
These are reference voltage output terminals.
VREFL is the reference voltage output terminal for the left channel, and VREFR is the reference voltage output terminal for
the right channel. Connect the same capacitors to these terminals. The starting time is set by changing the capacitance
connected to VREFL and VREFR terminals.
For the details, refer to "Pop noise reduction function" on page 9.
SLEEP (Pin No.24) [Digital-IN]
This is the operation shut off control terminal.
The terminal controls both channels at the same time. When SLEEP terminal is set at "H" level, all of the internal circuits
are placed in the shut off state, output is placed in the muted state, and the IC is placed in the sleep state.
At this time the power consumption is minimized, and warning signal (PROT terminal output) is set at "L" level.
When SLEEP terminal is set at "L" level, this IC goes into normal operation after sufficient time (starting time) to make
each reference voltage reaches a fixed potential.
4