YGV629 Datasheet, PDF (3/26 Pages) YAMAHA CORPORATION – VC1 Video Controller 1

YGV629









■ Block Diagram
Pattern
Memory I/F
MD[15:0]
MA[24:0]
MOE_N
MWE_N
RAHZ_N
CPU I/F
D[7:0]
PS[2:0]
CS_N
RD_N
WR_N
WAIT_N
READY_N
INT_N
SDIN
SCLK
SRI_N
RESET_N
CPU
Interface
Sprite
Rendering
Processor
Line Buffer
F
Sprite Plane Generator
Color Palette
General
Table
Registers
Line Plane Generator
Line
Rendering
Processor
Frame Data
Controller
CRTC
DAC
DAC
DAC
Monitor I/F
R, G, B
IREF
DR5-0
DG5-0
DB5-0
HCSYNC_N
VSYNC_N
BLANK_N
DOTCLK
FSC
YS_N
HSIN_N
VSIN_N
To all blocks
Clock
Gen.
Clock
XIN
XOUT
FILTER
DTCKIN
PLLCTL[5:0]]
■ Examples of System Composition
CPU
3
PS2-0
8
D7-0
25
MA24-0
16
MD15-0
MOE_N
VC1
MWE_N
XIN
XOUT
CSYNC_N
3
R,G,B
Pattern
Memory
max 256Mbit
LCD Monitor
-3-
4GV629A50