DS312 Datasheet, PDF (90/233 Pages) Xilinx, Inc – Absolute Maximum Ratings

Functional Description
R
shows the minimum required number of address lines parallel Flash PROM to hold additional data beyond just
between the FPGA and parallel Flash PROM. The actual FPGA configuration data. For example, the parallel Flash
number of address line required depends on the density of PROM can also contain the application code for a MicroBlaze
the attached parallel Flash PROM.
RISC processor core implemented within the Spartan-3E
A multiple-FPGA daisy-chained application requires a paral-
lel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-density
FPGA. After configuration, the MicroBlaze processor can
execute directly from external Flash or can copy the code to
other, faster system memory before executing the code.
Table 60: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Spartan-3E FPGA
Uncompressed
File Sizes (bits)
Smallest Usable
Parallel Flash PROM
Minimum Required
Address Lines
XC3S100E
581,344
1 Mbit
A[16:0]
XC3S250E
1,353,728
2 Mbit
A[17:0]
XC3S500E
2,270,208
4 Mbit
A[18:0]
XC3S1200E
3,841,184
4 Mbit
A[18:0]
XC3S1600E
5,969,696
8 Mbit
A[19:0]
Compatible Flash Families
The Spartan-3E BPI configuration interface operates with a
wide variety of x8 or x8/x16 parallel NOR Flash devices.
Table 61 provides a few Flash memory families that operate
with the Spartan-3E BPI interface. Consult the data sheet
for the desired parallel NOR Flash to determine its suitability
The basic timing requirements and waveforms are provided
in Byte Peripheral Interface (BPI) Configuration Timing
(Module 3).
Table 62: Maximum ConfigRate Settings for Parallel
Flash PROMs (Commercial Temperature Range)
Flash Read Access Time
Maximum ConfigRate
Setting
250 ns
3
115 ns
6
45 ns
12
Table 61: Compatible Parallel NOR Flash Families
Flash Vendor
Flash Memory Family
Numonyx
M29W, J3D StrataFlash
Atmel
AT29 / AT49
Spansion
S29
Macronix
MX29
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option.
Table 62 shows the maximum ConfigRate settings for vari-
ous typical PROM read access times over the Commercial
temperature operating range. See Byte Peripheral Inter-
face (BPI) Configuration Timing (Module 3) and UG332
for more detailed information. Despite using slower
ConfigRate settings, BPI mode is equally fast as the other
configuration modes. In BPI mode, data is accessed at the
ConfigRate frequency and internally serialized with an 8X
clock frequency.
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all
pins connected to the parallel Flash PROM are available as
user I/Os.
If not using the parallel Flash PROM after configuration,
drive LDC0 High to disable the PROM’s chip-select input.
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight
data lines, and the LDC2, LDC1, and HDC control pins.
Because all the interface pins are user I/Os after configura-
tion, the FPGA application can continue to use the interface
pins to communicate with the parallel Flash PROM. Parallel
Flash PROMs are available in densities ranging from 1 Mbit
up to 128 Mbits and beyond. However, a single Spartan-3E
FPGA requires less than 6 Mbits for configuration. If
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DS312-2 (v3.8) August 26, 2009
Product Specification