XCR3128 Datasheet, PDF (9/18 Pages) Xilinx, Inc – XCR3128: 128 Macrocell CPLD

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XCR3128: 128 Macrocell CPLD
Table 5: Programming Specifications
Symbol
Parameter
DC Parameters
V_CCP
I_CCP
V_IH
V_IL
V_SOL
V_SOH
TDO_I_OL
TDO_I_OH
V_CC supply program/verify
I_CC limit program/verify
Input voltage (High)
Input voltage (Low)
Output voltage (Low)
Output voltage (High)
Output current (Low)
Output current (High)
AC Parameters
f_MAX
PWE
CLK maximum frequency
Pulse width erase
PWP
Pulse width program
PWV
Pulse width verify
INIT
Initialization time
TMS_SU TMS setup time before TCK =
TDI_SU TDI setup time before TCK =
TMS_H TMS hold time after TCK =
TDI_H TDI hold time after TCK =
TDO_CO TDO valid after TCK Ο
Terminations
The CoolRunner XCR3128 CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR3128
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR3128 device be left uncon-
nected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10kΩ
pull-up resistors. These pins can be directly connected to
V_CC or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recom-
mended that 10kΩ pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Let-
Min.
Max.
Unit
3.0
3.6
V
200
mA
2.0
V
0.8
V
0.5
V
2.4
V
8
mA
-8
mA
10
MHz
100
ms
10
ms
10
µs
100
µs
10
ns
10
ns
25
ns
25
ns
40
ns
ting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the appli-
cation notes JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner CPLDs for more informa-
tion.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD’s and other integrated cir-
cuits. The Xilinx XCR3128 supports the following methods:
• PC parallel port
• Workstation or PC serial port
• Embedded processor
• Automated test equipment
• Third party programmers
• High-End JTAG and ISP tools
A Boundary-Scan Description Language (BSDL) descrip-
tion of the XCR3128 is also available from Xilinx for use in
test program development. For more details on JTAG and
ISP for the XCR3128, refer to the related application note:
JTAG and ISP Overview for Xilinx XPLA1 and XPLA2
CPLDs.
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DS034 (v1.2) August 10, 2000
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