XQR1701LCC44M Datasheet, PDF (5/11 Pages) Xilinx, Inc – Cascadable for storing longer or multiple bitstreams

R
QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR)
Vcc
DOUT
FPGA
MODES*
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
VCC
RESET
RESET
DIN
CCLK
DONE
INIT
3.3V
VPP
4.7K
VCC
DATA
VPP
CLK ^PROM
CE
CEO
OE/RESET
* For mode pin connections,
refer to the appropriate FPGA data sheet.
(Low Resets the Address Pointer)
CCLK
(Output)
DATA
CLK
CE
Cascaded
Serial
Memory
OE/RESET
D_IN
D_OUT
(Output)
DS027_02_060100
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
DS062 (v3.1) November 5, 2001
www.xilinx.com
5
Preliminary Product Specification
1-800-255-7778