XC73144 Datasheet, PDF (5/11 Pages) Xilinx, Inc – High-Performance EPLD

XC73144 CMOS EPLD
Fast Function Block (FFB) External AC Characteristics ³
Symbol Parameter
f_CF
Max count frequency ^{1, 2}
t_SUF
Fast input setup time before FCLK ↑ ¹
t_HF
Fast input hold time after FCLK ↑
t_COF
t_PDFO
t_PDFU
FCLK ↑ to output valid
Fast input to output valid ^{1, 2}
I/O to output valid ^{1, 2}
t_CWF
Fast clock pulse width
XC73144-7
(Com Only)
XC73144-10
(Com Only)
XC73144-12
(Com/Ind Only)
XC73144-15
Min Max Min Max Min
105.0
100.0
80.0
4.0
0
5.5
5.0
6.0
0
0
8.0
7.5
13.5
4.0
10.0
19.0
5.0
5.5
Max
9.0
12.0
22.0
Min Max Units
66.7
MHz
7.0
ns
0
ns
12.0 ns
15.0 ns
27.0 ns
6.0
ns
High-Density Function Block (FB) External AC Characteristics
Symbol
f_C
t_SU
t_H
t_CO
t_PSU
t_PH
t_PCO
t_PD
t_CW
t_PCW
Parameter
Max count frequency ^{1, 2}
I/O setup time before FCLK ↑ ^{1, 2}
I/O hold time after FCLK ↑
FCLK ↑ to output valid
I/O setup time before p-term clock ↑ ²
I/O hold time after p-term clock ↑
P-term clock ↑ to output valid
I/O to output valid ^{1, 2}
Fast clock pulse width
P-term clock pulse width
XC73144-7
(Com Only)
XC73144-10
(Com Only)
XC73144-12
(Com/Ind Only)
XC73144-15
Min Max Min Max Min Max Min Max Units
83.3
62.5
55.6
45.5
MHz
12.0
16.0
18.0
22.0
ns
0
0
0
0
ns
7.0
4.0
0
10.0
6.0
0
12.0
7.0
0
15.0 ns
9.0
ns
0
ns
15.0
18.0
4.0
20.0
25.0
5.0
23.0
30.0
5.5
28.0 ns
36.0 ns
6.0
ns
5.0
6.0
7.5
8.5
ns
Preliminary
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of t_FLOGILP – t_FLOGI or t _LOGILP – t_LOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
2-69