DS598 Datasheet, PDF (5/9 Pages) Xilinx, Inc – Optimized for high-performance 3.3V systems

R
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
T_IN
Input buffer delay
T_GCK GCK buffer delay
T_GSR GSR buffer delay
T_GTS
GTS buffer delay
T_OUT Output buffer delay
T_EN
Output buffer enable/disable delay
Product Term Control Delays
T_PTCK Product term clock delay
T_PTSR Product term set/reset delay
T_PTTS Product term 3-state delay
Internal Register and Combinatorial Delays
T_PDI
Combinatorial logic propagation delay
T_SUI
Register setup time
T_HI
Register hold time
T_ECSU Register clock enable setup time
T_ECHO Register clock enable hold time
T_COI
Register clock to output valid time
T_AOI
Register async. S/R to output delay
T_RAI
Register async. S/R recover before clock
T_LOGI Internal logic delay
Feedback Delays
T_F
Fast CONNECT II feedback delay
Time Adders
T_PTA
T_SLEW
Incremental product term allocator delay
Slew-rate limited delay
XA9536XL Automotive CPLD
XA9536XL-15
Min
Max
-
3.5
-
1.8
-
4.5
-
7.0
-
3.0
-
0
-
2.7
-
1.8
-
7.5
-
1.7
3.0
-
3.5
-
3.0
-
3.5
-
-
1.0
-
7.0
10.0
-
-
7.3
-
4.2
-
1.0
-
4.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS598 (v1.1) April 3, 2007
www.xilinx.com
5
Product Specification