DS066 Datasheet, PDF (5/10 Pages) Xilinx, Inc – 5V in-system programmable

– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC95108 In-System Programmable CPLD
Internal Timing Parameters
XC95108-7 XC95108-10 XC95108-15
Symbol
Parameter
Min Max Min Max Min Max
Buffer Delays
T_IN Input buffer delay
T_GCK GCK buffer delay
T_GSR GSR buffer delay
T_GTS GTS buffer delay
T_OUT Output buffer delay
T_EN Output buffer enable/disable delay
Product Term Control Delays
-
2.5
-
3.5
-
4.5
-
1.5
-
2.5
-
3.0
-
4.5
-
6.0
-
7.5
-
5.5
-
6.0
- 11.0
-
2.5
-
3.0
-
4.5
-
0
-
0
-
0
T_PTCK Product term clock delay
T_PTSR Product term set/reset delay
T_PTTS Product term 3-state delay
Internal Register and Combinatorial Delays
-
3.0
-
3.0
-
2.5
-
2.0
-
2.5
-
3.0
-
4.5
-
3.5
-
5.0
T_PDI Combinatorial logic propagation delay
-
0.5
-
1.0
-
3.0
T_SUI Register setup time
1.5
-
2.5
-
3.5
-
T_HI Register hold time
3.0
-
3.5
-
4.5
-
T_COI Register clock to output valid time
-
0.5
-
0.5
-
0.5
T_AOI Register async. S/R to output delay
-
6.5
-
7.0
-
8.0
T_RAI Register async. S/R recover before clock 7.5
- 10.0 - 10.0 -
T_LOGI Internal logic delay
-
2.0
-
2.5
-
3.0
T_LOGILP Internal low power logic delay
- 10.0 - 11.0 - 11.5
Feedback Delays
T_F FastCONNECT feedback delay
T_LF Function block local feedback delay
Time Adders
-
8.0
-
9.5
- 11.0
-
4.0
-
3.5
-
3.5
T_PTA(1) Incremental product term allocator delay
-
1.0
-
1.0
-
1.0
T_SLEW Slew-rate limited delay
-
4.0
-
4.5
-
5.0
Notes:
1. T_PTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
XC95108-20
Min Max Units
-
6.5 ns
-
3.0 ns
-
9.5 ns
- 16.0 ns
-
6.5 ns
-
0
ns
-
2.5 ns
-
3.0 ns
-
5.0 ns
-
4.0 ns
3.5
-
ns
6.5
-
ns
-
0.5 ns
-
8.0 ns
10.0 -
ns
-
3.0 ns
- 11.5 ns
- 13.0 ns
-
5.0 ns
-
1.5 ns
-
5.5 ns
DS066 (v5.0) May 17, 2013
www.xilinx.com
5
Product Specification