DS181 Datasheet, PDF (40/62 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 38: PLL Specification (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.95V
0.9V
Units
-3
-2/-2LE
-1
-1LI
-2LE
F_DCK
DCLK frequency
200.00 200.00 200.00 200.00 100.00 MHz, Max
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
Device Pin-to-Pin Output Parameter Guidelines
Table 39: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)⁽¹⁾
Speed Grade
Symbol
Description
Device
1.0V
0.95V
-3 -2/-2LE -1 -1M/-1Q -1LI
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
T_ICKOF
Clock-capable clock input and OUTFF at
pins/banks closest to the BUFGs without
MMCM/PLL (near clock region)⁽²⁾
XC7A12T
XC7A15T
XC7A25T
4.97 5.55 6.44
N/A
6.44
5.10 5.70 6.61
N/A
6.61
4.97 5.55 6.44
N/A
6.44
XC7A35T
5.10 5.70 6.61
N/A
6.61
XC7A50T
5.10 5.70 6.61
N/A
6.61
XC7A75T
5.14 5.74 6.72
N/A
6.72
XC7A100T 5.14 5.74 6.72
N/A
6.72
XC7A200T 5.47 6.11 7.16
N/A
7.16
XA7A15T
N/A 5.70 6.61 6.61
N/A
XA7A35T
N/A 5.70 6.61 6.61
N/A
XA7A50T
N/A 5.70 6.61 6.61
N/A
XA7A75T
N/A 5.74 6.72 6.72
N/A
XA7A100T
N/A
5.74 6.72
6.72
N/A
XQ7A50T
N/A 5.70 6.61
6.61
6.61
XQ7A100T
N/A 5.74 6.72
6.72
6.72
XQ7A200T
N/A 6.11 7.16
7.16
7.16
0.9V Units
-2LE
ns
7.56 ns
ns
7.56 ns
7.56 ns
7.62 ns
7.62 ns
8.08 ns
N/A ns
N/A ns
N/A ns
N/A ns
N/A ns
N/A ns
N/A ns
N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475).
DS181 (v1.21) September 27, 2016
Product Specification
www.xilinx.com
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