VIRTEX-5 Datasheet, PDF (34/72 Pages) Xilinx, Inc – Virtex-5 Family Overview

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Virtex-5 Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics Input Delay Switching Characteristics
Table 37: OSERDES Switching Characteristics
Symbol
Setup/Hold
T_{OSDCK_D}/T_{OSCKD_D}
Description
D input Setup/Hold with respect to CLKDIV
T_{OSDCK_T}/T_{OSCKD_T(1)}
T input Setup/Hold with respect to CLK
T_{OSDCK_T2}/T_{OSCKD_T2(1)}
T input Setup/Hold with respect to CLKDIV
T_{OSCCK_OCE}/T_{OSCKC_OCE}
OCE input Setup/Hold with respect to CLK
T_{OSCCK_S}
T_{OSCCK_TCE}/T_{OSCKC_TCE}
SR (Reset) input Setup with respect to CLKDIV
TCE input Setup/Hold with respect to CLK
Sequential Delays
T_{OSCKO_OQ}
Clock to out from CLK to OQ
T_{OSCKO_TQ}
Clock to out from CLK to TQ
Combinatorial
T_{OSDO_TTQ}
T input to TQ Out
T_{OSCO_OQ}
Asynchronous Reset to OQ
T_{OSCO_TQ}
Asynchronous Reset to TQ
Notes:
1. T_{OSDCK_T2} and T_{OSCKD_T2} are reported as T_{OSDCK_T}/T_{OSCKD_T} in TRACE report.
Speed Grade
-3
-2
-1
Units
0.21
0.24
0.30
ns
–0.02 –0.02 –0.02
0.28
0.34
0.41
ns
–0.18 –0.18 –0.18
0.21
0.24
0.28
ns
–0.03 –0.03 –0.03
0.16
0.19
0.23
ns
–0.07 –0.07 –0.07
0.52
0.58
0.70
ns
0.20
0.23
0.29
ns
–0.06 –0.06 –0.06
0.59
0.60
0.61
ns
0.61
0.62
0.62
ns
0.62
0.70
0.83
ns
1.57
1.82
2.19
ns
1.63
1.89
2.27
ns
DS202 (v3.6) November 5, 2007
www.xilinx.com
Advance Product Specification
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