EN094 Datasheet, PDF (2/2 Pages) Xilinx, Inc – Spartan-3E XC3S1600E FPGA Errata

Spartan-3E XC3S1600E FPGA Errata
R
.
Table 2: Affected Pins
Package
FG(G)320
FG(G)400
FG(G)484
A20⁽¹⁾
R14
V16
Y18
A21⁽²⁾
T14
U16
W18
A22⁽²⁾
R13
Y14
AB17
A23⁽²⁾
P13
Y15
AA17
Notes:
1. In FG(G)400 and FG(G)484, pin name IO_LxxN_2/A20, not ball location A20.
2. In FG(G)484, pin names IO_L38P_2/A21, IO_L35N_2/A22, and IO_L35P_2/A23, not
ball locations A21, A22, A23.
Workaround
Customers who use the Persist option in the Bitstream Generator and who use a parallel configuration mode must
not use the affected I/O pins in the design. No I/O should be placed on these pins by the user, and the pins need to
be prohibited for the tools by using the Prohibit constraint on each pin. This constraint can be specified in the User
Constraints File (UCF) with the following syntax:
CONFIG PROHIBIT=R14,T14,R13,P13;
Alternatively, consider not using Persist if post-configuration Readback is not required.
These pins will be added to the list of pins that Persist in the documentation. In ISE software version 10.1 and later,
an error message will be provided by the bitstream generator if Persist is used and the design uses these four pins.
Additional Questions or Clarifications
All other device functionality and timing meet the data sheet specifications. For questions, please contact Xilinx Technical
Support http://www.xilinx.com/support/clearexpress/websupport.htm or your Xilinx sales representative,
http://www.xilinx.com/company/contact.htm.
Obtaining Errata Notification Updates
If this document is printed or saved locally, please check for the most recent release, available to registered users on the
Xilinx web site at http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Errata. To receive an e-mail alert
when this document changes, sign up at http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=18815.
Applicable Documents
These errata apply to the following XC3S1600E documents:
• DS312: Spartan^TM-3E FPGA Family Data Sheet
www.xilinx.com/bvdocs/publications/ds312.pdf
• UG331: Spartan-3 Generation FPGA User Guide
www.xilinx.com/bvdocs/userguides/ug331.pdf
• UG332: Spartan-3 Generation Configuration User Guide
www.xilinx.com/bvdocs/userguides/ug332.pdf
Revision History
The following table shows the revision history for this document.
Date
10/19/07
Version
1.0
Initial version
Description
2
www.xilinx.com
EN094 (v1.0) October 19, 2007
Errata Notice