DS022-1 Datasheet, PDF (2/5 Pages) Xilinx, Inc – Field Programmable Gate Arrays

Virtex™-E 1.8 V Field Programmable Gate Arrays
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Table 1: Virtex-E Field-Programmable Gate Array Family Members
Device
System
Gates
Logic
Gates
CLB
Array
Logic Differential
Cells I/O Pairs
XCV50E
71,693
20,736
16 x 24 1,728
83
XCV100E
128,236
32,400
20 x 30 2,700
83
XCV200E
306,393
63,504
28 x 42 5,292
119
XCV300E
411,955
82,944
32 x 48 6,912
137
XCV400E
569,952
129,600
40 x 60 10,800
183
XCV600E
985,882
186,624
48 x 72 15,552
247
XCV1000E 1,569,178
331,776
64 x 96 27,648
281
XCV1600E 2,188,742 419,904 72 x 108 34,992
344
XCV2000E 2,541,952 518,400 80 x 120 43,200
344
XCV2600E 3,263,755 685,584 92 x 138 57,132
344
XCV3200E 4,074,387 876,096 104 x 156 73,008
344
User
I/O
176
196
284
316
404
512
660
724
804
804
804
BlockRAM
Bits
65,536
81,920
114,688
131,072
163,840
294,912
393,216
589,824
655,360
753,664
851,968
Distributed
RAM Bits
24,576
38,400
75,264
98,304
153,600
221,184
393,216
497,664
614,400
812,544
1,038,336
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.
I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchro-
nous system performance up to 240 MHz using sin-
gled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.
Virtex-E devices have up to 640 Kb of faster (250 MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each indi-
vidual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.
V_CCINT, the supply voltage for the internal logic and mem-
ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
m processing and 0.18 m design rules have resulted in
smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an
W external 100 resistor. PCI 5 V is not supported. With the
addition of appropriate external resistors, any pin can toler-
ate any voltage desired.
Banking rules are different. With Virtex devices, all input
buffers are powered by V_CCINT. With Virtex-E devices, the
LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage V_CCO.
The Virtex-E family is not bitstream-compatible with the Vir-
tex family, but Virtex designs can be compiled into equiva-
lent Virtex-E devices.
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions. See the data sheet pinout section for details.
General Description
The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
m aggressive 6-layer metal 0.18 m CMOS process. These
advances make Virtex-E FPGAs powerful and flexible alter-
natives to mask-programmed gate arrays. The Virtex-E fam-
ily includes the nine members in Table 1.
Building on experience gained from Virtex FPGAs, the
Virtex-E family is an evolutionary step forward in program-
mable logic design. Combining a wide variety of program-
mable system features, a rich hierarchy of fast, flexible
interconnect resources, and advanced process technology,
the Virtex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
Module 1 of 4
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DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification