XCR5128C Datasheet, PDF (15/19 Pages) Xilinx, Inc – High speed pin-to-pin delays of 7.5 ns

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R
XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
Switching Characteristics
V_CC
S1
R1
V_IN
V_OUT
R2
C1
S2
COMPONENT
R1
R2
C1
VALUES
390Ω
390Ω
35 pF
MEASUREMENT
S1
S2
t_PZH
Open
Closed
t_PZL
Closed
Closed
t_P
Closed
Closed
Note: For tPHZ and tPLZ C = 5 pF, and 3-state levels are
measured 0.5V from steady state active level.
V_DD = 5V, 25°C
7.0
6.9
6.8
6.7
t_{PD_PAL 6.6}
(ns)
6.5
6.4
6.3
6.2
6.1
6.0
12
4
8
12
NUMBER OF OUTPUTS SWITCHING
Figure 6: t_{PD_PAL} vs. Outputs Switching
16
SP00619
Voltage Waveform
SP00618
+3.0V
90%
0V
1.5ns
tR
tF
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
10%
1.5ns
SP00368
Table 7: t_{PD_PAL} vs. Number of Outputs Switching
(V_CC = 5V, 25°C)
Number Of 1
2
4
8
12
16
Outputs
Typical (ns) 6.362 6.432 6.49 6.562 6.63 6.705
15
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DS042 (v1.3) October 9, 2000
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