XCCACE-TQ144 Datasheet, PDF (15/69 Pages) Xilinx, Inc – Non-volatile system solution

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System ACE CompactFlash Solution
Data Buffer Read Cycle Ready Timing
When the data buffer is in read mode and the last data word
is read from the buffer, the data buffer ready signal will go
inactive (MPBRDY = LOW) two clock cycles following the
last clock cycle that the output enable is active (MPOE =
LOW). Any attempt to read data out of an “empty” data
buffer (MPOE = LOW while MPBRDY = LOW) results in
invalid data. Valid and invalid data buffer reads are shown in
Figure 14.
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
MPBRDY
50ns
Cycle 0
Cycle 1
100ns
Cycle 2
150ns
Cycle 3
Cycle 4
200ns
Cycle 5
Cycle 6
250
Cycle 7
tH
tH
tSA
tSA
DATABUFREG ADDRESS
DATABUFREG ADDRESS
tDD
tDD
tDD
tDD
VALID DATA
INVALID DATA
tH
tDOE
tDOE
tSCE
tSWE
tH
tDOE
tSOE
tDOE
tH
tSOE
tDOE
tDOE
tH
tH
tH
tSOE
tSOE
tDBRDY
DS080_18_020101
Figure 14: Valid and Invalid Reads From DATABUFREG Data Buffer
DS080 (v1.4) January 3, 2002
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