XCV405E Datasheet, PDF (1/4 Pages) Xilinx, Inc – Fast, Extended Block RAM, 1.8 V FPGA Family

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Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
DS025-1 (v1.4) April 2, 2001
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Features
• Fast, Extended Block RAM, 1.8 V FPGA Family
- 560 Kb and 1,120 Kb embedded block RAM
- 130 MHz internal performance (four LUT levels)
- PCI compliant 3.3 V, 32/64-bit, 33/66-MHz
• Sophisticated SelectRAM+™ Memory Hierarchy
- 294 Kb of internal configurable distributed RAM
- Up to 1,120 Kb of synchronous internal block RAM
- True Dual-Port™ block RAM
- Memory bandwidth up to 2.24 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
external memories
· 200 MHz ZBT* SRAMs
· 200 Mb/s DDR SDRAMs
• Highly Flexible SelectIO+™ Technology
- Supports 20 high-performance interface standards
- Up to 556 singled-ended I/Os or up to 201
differential I/O pairs for an aggregate bandwidth of
>100 Gb/s
• Complete Industry-Standard Differential Signalling
Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Al I/O signals can be input, output, or bi-directional
* ZBT is a trademark of Integrated Device Technology, Inc.
Introduction
The Virtex™-E Extended Memory (Virtex-EM) family of
FPGAs is an extension of the highly successful Virtex-E
family architecture. The Virtex-EM family (devices shown in
Table 1) includes all of the features of Virtex-E, plus addi-
tional block RAM, useful for applications such as network
switches and high-performance video graphic systems.
Xilinx developed the Virtex-EM product family to enable
customers to design systems requiring high memory band-
width, such as 160 Gb/s network switches. Unlike traditional
ASIC devices, this family also supports fast time-to-market
delivery, because the development engineering is already
completed. Just complete the design and program the
device. There is no NRE, no silicon production cycles, and no
Preliminary Product Specification
- LVPECL and LVDS clock inputs for 300+ MHz
clocks
• Proprietary High-Performance SelectLink™
Technology
- 80 Gb/s chip-to-chip communication link
- Support for Double Data Rate (DDR) interface
- Web-based HDL generation methodology
• Eight Fully Digital Delay-Locked Loops (DLLs)
• IEEE 1149.1 boundary-scan logic
• Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
- Internet Team Design (Xilinx iTD™) tool ideal for
million-plus gate density designs
- Wide selection of PC or workstation platforms
• SRAM-based In-System Configuration
- Unlimited re-programmability
• Advanced Packaging Options
- 1.0 mm FG676 and FG900
- 1.27 mm BG560
m • 0.18 m 6-layer Metal Process with Copper
Interconnect
• 100% Factory Tested
additional delays for design re-work. In addition, designers
can update the design over a network at any time, providing
product upgrades or updates to customers even sooner.
The Virtex-EM family is the result of more than fifteen years
of FPGA design experience. Xilinx has a history of support-
ing customer applications by providing the highest level of
logic, RAM, and features available in the industry. The Vir-
tex-EM family, first FPGAs to deploy copper interconnect,
offers the performance and high memory bandwidth for
advanced system integration without the initial investment,
long development cycles, and inventory risk expected in tra-
ditional ASIC development.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS025-1 (v1.4) April 2, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
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