XCR3512XL Datasheet, PDF (1/14 Pages) Xilinx, Inc – Lowest power 512 macrocell CPLD

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XCR3512XL: 512 Macrocell CPLD
DS081 (v1.2) September 4, 2001
0 14 _{Advance Product Specification}
Features
• Lowest power 512 macrocell CPLD
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 127 MHz
• 512 macrocells with 12,800 usable gates
• Available in small footprint packages
- 208-pin PQFP (180 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (260 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- FZP™ CMOS design technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial grade voltage
range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 32 function blocks provide
12,800 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS™ Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the I_CC vs. Frequency of our
XCR3512XL TotalCMOS CPLD (data taken with 32
up/down, loadable 16-bit counters at 3.3V, 25°C).
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120
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80
60
40
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20 40 60 80 100 120 140 160
Frequency (MHz)
DS024_01_112700
Figure 1: XCR3512XL Typical I_CC vs. Frequency at V_CC
= 3.3V, 25°C
Table 1: Typical I_CC vs. Frequency at V_CC = 3.3V, 25°C
Frequency (MHz)
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1
10
20
Typical I_CC (mA)
TBD TBD TBD TBD
40
TBD
60
TBD
80
TBD
100
TBD
120
TBD
140
TBD
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DS081 (v1.2) September 4, 2001
www.xilinx.com
1
Advance Product Specification
1-800-255-7778