XCR3384XL Datasheet, PDF (1/12 Pages) Xilinx, Inc – Lowest power 384 macrocell CPLD

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XCR3384XL: 384 Macrocell CPLD
DS024 (v1.3) August 10, 2001
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Features
• Lowest power 384 macrocell CPLD
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 127 MHz
• 384 macrocells with 9,600 usable gates
• Available in small footprint packages
- 144-pin TQFP (118 user I/O)
- 208-pin PQFP (172 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (220 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- FZP™ CMOS design technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial grade voltage
range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 24 function blocks provide
9,600 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS™ Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the I_CC vs. Frequency of our
XCR3384XL TotalCMOS CPLD (data taken with 24
up/down, loadable 16-bit counters at 3.3V, 25°C).
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60
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20 40 60 80 100 120 140 160
Frequency (MHz)
DS024_01_112700
Figure 1: XCR3384XL Typical I_CC vs. Frequency at
V_CC = 3.3V, 25°C
Table 1: Typical I_CC vs. Frequency at V_CC = 3.3V, 25°C
Frequency (MHz)
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1
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20
40
60
80
100 120 140
Typical I_CC (mA)
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
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DS024 (v1.3) August 10, 2001
www.xilinx.com
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Advance Product Specification
1-800-255-7778