XCR3032XL Datasheet, PDF (1/12 Pages) Xilinx, Inc – CoolRunner XPLA3 CPLD

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CoolRunner XPLA3 CPLD
DS012 (v2.5) May 26, 2009
0 14 _{Product Specification}
Features
• Fast Zero Power (FZP) design technique provides
ultra-low power and very high speed
- Typical Standby Current of 17 to 18 μA at 25°C
• Innovative CoolRunner™ XPLA3 architecture
combines high speed with extreme flexibility
• Based on industry's first TotalCMOS PLD — both
CMOS design and process technologies
• Advanced 0.35μ five layer metal EEPROM process
- 1,000 erase/program cycles guaranteed
- 20 years data retention guaranteed
• 3V, In-System Programmable (ISP) using JTAG IEEE
1149.1 interface
- Full Boundary-Scan Test (IEEE 1149.1)
- Fast programming times
• Support for complex asynchronous clocking
- 16 product term clocks and four local control term
clocks per function block
- Four global clocks and one universal control term
clock per device
• Excellent pin retention during design changes
• Available in commercial grade and extended voltage
(2.7V to 3.6V) industrial grade
• 5V tolerant I/O pins
• Input register setup time of 2.5 ns
• Single pass logic expandable to 48 product terms
• High-speed pin-to-pin delays of 5.0 ns
• Slew rate control per output
• 100% routable
• Security bit prevents unauthorized access
• Supports hot-plugging capability
• Design entry/verification using Xilinx or industry
standard CAE tools
• Innovative Control Term structure provides:
- Asynchronous macrocell clocking
- Asynchronous macrocell register preset/reset
- Clock enable control per macrocell
• Four output enable controls per function block
• Foldback NAND for synthesis optimization
• Universal 3-state which facilitates "bed of nails" testing
• Available in Chip-scale BGA, Fineline BGA, and QFP
packages. Pb-free available for most package types.
See Xilinx Packaging for more information.
Table 1: CoolRunner XPLA3 Device Family
XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL
Macrocells
32
64
128
256
384
512
Usable Gates
750
1,500
3,000
6,000
9,000
12,000
Registers
32
64
128
256
384
512
T_PD (ns)
4.5
5.5
5.5
7.0
7.0
7.0
T_SU (ns)
3.0
3.5
3.5
4.3
4.3
3.8
T_CO (ns)
3.5
4
4
4.5
4.5
5.0
F_system (MHz)
213
192
175
154
135
135
I_CCSB (μA)
17
17
17
18
18
18
Table 2: CoolRunner XPLA3 Packages and User I/O Pins
XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL
44-pin VQFP
36
36
-
-
-
-
48-pin 0.8mm CSP
36
40
-
-
-
-
56-pin 0.5mm CSP
-
48
-
-
-
-
100-pin VQFP
-
68
84
-
-
-
144-pin 0.8mm CSP
-
-
108
-
-
-
144-pin TQFP
-
-
108
120
118⁽¹⁾
-
208-pin PQFP
-
-
-
164
172
180
256-pin Fineline BGA
-
-
-
164
212
212
280-pin 0.8mm CSP
-
-
-
164
-
-
324-pin Fineline BGA
-
-
-
-
220
260
1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the CoolRunner XPLA3 family in the TQ144 package.
2. Most packages are available in Pb-Free option. See individual data sheets for more details.
3. The 44-pin PLCC package is discontinued per XCN07022.
© 2000–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS012 (v2.5) May 26, 2009
www.xilinx.com
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Product Specification