XCR3032XL-5VQ44C Datasheet, PDF (1/9 Pages) Xilinx, Inc – XCR3032XL 32 Macrocell CPLD

0
R
XCR3032XL 32 Macrocell CPLD
DS023 (v2.2) September 15, 2008
0 14 _{Product Specification}
Features
• Low power 3.3V 32 macrocell CPLD
• 4.5 ns pin-to-pin logic delays
• System frequencies up to 213 MHz
• 32 macrocells with 750 usable gates
• Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/Os)
• Optimized for 3.3V systems
- Ultra-low power operation
- Typical Standby Current of 17 μA at 25°C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power (FZP) CMOS technology
- 3.3V PCI electrical specification compatible
outputs (no internal clamp diode on any input or
I/O, no minimum clock input capacitance)
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to the CoolRunner XPLA3 family data sheet
(DS012) for architecture description
Description
The CoolRunner™ XPLA3 XCR3032XL device is a 3.3V,
32-macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of two function blocks provide 750 usable gates.
Pin-to-pin propagation delays are as fast as 4.5 ns with a
maximum system frequency of 213 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,
both in process technology and design technique. Xilinx®
CPLDs employ a cascade of CMOS gates to implement its
sum of products instead of the traditional sense amp
approach. This CMOS gate implementation allows Xilinx to
offer CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, one must
have low performance. Refer to Figure 1 and Table 1 show-
ing the I_CC vs. Frequency of the XCR3032XL TotalCMOS
CPLD (data taken with two resetable up/down, 16-bit
counters at 3.3V, 25° C).
20
15
10
5
0
0 20 40 60 80 100 120 140 160 180 200
Frequency (MHz)
DS023_01_080101
Figure 1: I_CC vs. Frequency at V_CC = 3.3V, 25°C
Table 1: I_CC vs. Frequency (V_CC = 3.3V, 25°C)
Frequency (MHz)
0
1
5
10
20
Typical I_CC (mA)
0.017
0.13
0.54
1.06
2.09
50
100
200
5.2
10.26
20.3
© 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v2.2) September 15, 2008
www.xilinx.com
1
Product Specification