XCN07021 Datasheet, PDF (1/2 Pages) Xilinx, Inc – Data Sheet Pin-to-Pin

XCN07021 (v1.0) December 24, 2007
Data Sheet Pin-to-Pin
Specification Change for the
Virtex-5 Family
For Your Information
Overview
The purpose of this notification is to communicate a data sheet pin-to-pin specification change for the Virtex™-5 family.
Description
Pin-to-Pin Data Sheet change: For the Virtex-5 family, some pin-to-pin parameters have been changed to improve the
accuracy of the generated timing report. A setup/hold and clock to out timing change has been implemented in ISE™ 9.2.04i
in conjunction with Speed File v1.58 and the Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Data Sheet
(DS202 v3.7):
• Designs using PLLs to capture data should be re-timed using speed file v1.58 in conjunction with ISE 9.2.04i.
• XC5VSX95T-2 designs using DCM in System-Synchronous mode should be re-timed using speed file v1.58 in
conjunction with ISE 9.2.04i.
Note: If your design does not meet the above criteria, no action is required.
DS202 v3.7
Tables
Change
Table 66
Global Clock Setup and Hold with
DCM in System-Synchronous Mode
Tables 68 and 61
Global Clock Setup and Hold
(and Clock to Out) With PLL in
System-Synchronous Mode
Tables 69 and 62
Global Clock Setup and Hold
(and Clock to Out) With PLL in
Source-Synchronous Mode
Global Clock Setup and Hold
Tables 70 and 63 (and Clock to Out) With DCM and PLL
in System-Synchronous Mode
Global Clock Setup and Hold
Tables 71 and 64 (and Clock to Out) With DCM and PLL
in Source-Synchronous Mode
Affected Devices
Details
SX95T-2 setup
All devices and
speed grades
All devices and
speed grades
All devices and
speed grades
All devices and
speed grades
Only the SX95T-2 is changing by
~200 ps, consult DS202 v3.7 for
specific values
Average change is +200 ps to setup,
consult DS202 v3.7 for specific
values
There will be a minor optimization of
the setup and hold times (less than
100 ps), consult DS202 v3.7 for
specific values
Average change is +200 ps to setup,
consult DS202 v3.7 for specific
values
Average change is +200 ps to setup,
consult DS202 v3.7 for specific
values
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
XCN07021 (v1.0) December 24, 2007
www.xilinx.com
1