XC95288XL Datasheet, PDF (1/11 Pages) Xilinx, Inc – Available in small footprint packages

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XC95288XL High Performance
CPLD
DS055 (v1.5) June 20, 2002
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Features
• 6 ns pin-to-pin logic delays
• System frequency up to 208 MHz
• 288 macrocells with 6,400 usable gates
• Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I_CC, the following equation may be
used:
I_CC(mA) = MC_HS(0.175*PT_HS + 0.345) + MC_LP(0.052*PT_LP
+ 0.272) + 0.04 * MC_TOG(MC_HS +MC_LP)* f
where:
MC_HS = # macrocells in high-speed configuration
PT_HS = average number of high-speed product terms
per macrocell
MC_LP = # macrocells in low power configuration
PT_LP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I_CC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
550
208 MHz
500
450
400
350
High ^Performance
300
250
200
Low ^Power
94 MHz
150
100
50
0
50
100
150
200
250
Clock Frequency (MHz)
DS055_01_121501
Figure 1: Typical I_CC vs. Frequency for XC95288XL
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DS055 (v1.5) June 20, 2002
www.xilinx.com
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Product Specification
1-800-255-7778