XC9500 Datasheet, PDF (1/16 Pages) Xilinx, Inc – XC9500 In-System Programmable CPLD Family

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XC9500 In-System Programmable
CPLD Family
DS063 (v5.1) September 22, 2003
0 0 _{Product Specification}
Features
• High-performance
- 5 ns pin-to-pin logic delays on all pins
- f_CNT to 125 MHz
• Large density range
- 36 to 288 macrocells with 800 to 6,400 usable
gates
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
- Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
- Programmable power reduction mode in each
macrocell
- Slew rate control on individual outputs
- User programmable ground pin capability
- Extended pattern security features for design
protection
- High-drive 24 mA outputs
- 3.3V or 5V I/O capability
- Advanced CMOS 5V Fast FLASH™ technology
- Supports parallel programming of multiple XC9500
devices
Family Overview
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan sup-
port is also included on all family members.
As shown in Table 1, logic density of the XC9500 devices
ranges from 800 to over 6,400 usable gates with 36 to 288
registers, respectively. Multiple package options and asso-
ciated I/O capacity are shown in Table 2. The XC9500 fam-
ily is fully pin-compatible allowing easy design migration
across multiple density options in a given package footprint.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3V or 5V operation. All
outputs provide 24 mA drive.
Table 1: XC9500 Device Family
XC9536
XC9572
XC95108
XC95144
XC95216
Macrocells
36
72
108
144
216
Usable Gates
800
1,600
2,400
3,200
4,800
Registers
36
72
108
144
216
T_PD (ns)
5
7.5
7.5
7.5
10
T_SU (ns)
3.5
4.5
4.5
4.5
6.0
T_CO (ns)
f_CNT (MHz)⁽¹⁾
4.0
4.5
4.5
4.5
6.0
100
125
125
125
111.1
f_SYSTEM (MHz)⁽²⁾
100
83.3
83.3
83.3
66.7
Notes:
1. f_CNT = Operating frequency for 16-bit counters.
2. f_SYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.
XC95288
288
6,400
288
15
8.0
8.0
92.2
56.6
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DS063 (v5.1) September 22, 2003
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Product Specification
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