XA2S200E-6FT256Q Datasheet, PDF (1/6 Pages) Xilinx, Inc – Automotive XA Product Family

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DS106-1 (v1.7) October 18, 2004
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Spartan-IIE 1.8V FPGA
Automotive XA Product Family:
Introduction and Ordering
0 0 _{Preliminary Product Specification}
Introduction
The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Pro-
grammable Gate Array family is specifically designed to
meet the needs of high-volume, cost-sensitive automotive
electronic applications. The family gives users high perfor-
mance, abundant logic resources, and a rich feature set, all
at an exceptionally low price. The five-member family offers
densities ranging from 50,000 to 300,000 system gates, as
shown in Table 1. System performance is supported beyond
200 MHz.
Spartan-IIE devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the proven Virtex™-E platform. Features include block
RAM (to 64K bits), distributed RAM (to 98,304 bits), 19
selectable I/O standards, and four DLLs (Delay-Locked
Loops). Fast, predictable interconnect means that succes-
sive design iterations continue to meet timing requirements.
XA devices are available in both the extended-temperature
Q-grade (-40°C to +125°C) and industrial I-grade (-40°C to
+100°C) and are qualified to the industry-recognized
AEC-Q100 standard.
The XA Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial
cost, lengthy development cycles, and inherent risk of con-
ventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade
• Guaranteed to meet full electrical specifications over
T_J = –40°C to +125°C
• Second generation ASIC replacement technology
- Densities as high as 6,912 logic cells with up to
300,000 system gates
- Very low cost
• System-level features
- SelectRAM+™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM
· Fast interfaces to external RAM
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
· Eliminate clock distribution delay
· Multiply, divide, or phase shift
- Four primary low-skew global clock distribution
nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Low-cost packages available in all densities
- 19 high-performance interface standards
· LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
· LVDS and LVPECL differential I/O
- Up to 120 differential I/O pairs that can be input,
output, or bidirectional
• Fully supported by powerful Xilinx ISE development
system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
- Extensive IP library including DSP functions
Table 1: XA Spartan-IIE FPGA Family Members
Device
Logic
Cells
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(R x C)
Maximum Maximum
Total Available Differential
CLBs User I/O⁽¹⁾ I/O Pairs
XA2S50E 1,728
23,000 - 50,000
16 x 24 384
102
83
XA2S100E 2,700 37,000 - 100,000 20 x 30 600
102
86
XA2S150E 3,888 52,000 - 150,000 24 x 36 864
182
114
XA2S200E 5,292 71,000 - 200,000 28 x 42 1,176
182
120
XA2S300E 6,912 93,000 - 300,000 32 x 48 1,536
182
120
Notes:
1. User I/O counts include the four global clock/user input pins. See details in Table 3, page 5
Distributed
RAM Bits
24,576
38,400
55,296
75,264
98,304
Block
RAM Bits
32K
40K
48K
56K
64K
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DS106-1 (v1.7) October 18, 2004
www.xilinx.com
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Preliminary Product Specification
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