OPB16450UART Datasheet, PDF (1/15 Pages) Xilinx, Inc – This document provides the specification

0
OPB 16450 UART
DS433 August 18, 2004
0 0 _{Product Specification}
Introduction
This document provides the specification for the OPB Uni-
versal Asynchronous Receiver/Transmitter (UART) Intellec-
tual Property (IP).
The UART described in this document has been designed
incorporating the features described in National Semicon-
ductor PC16550D UART with FIFOs data sheet (June,
1995), (http://www.national.com/pf/PC/PC16550D.html).
The National Semiconductor PC16550D data sheet is refer-
enced throughout this document and should be used as the
authoritative specification. Differences between the
National Semiconductor implementation and the OPB
UART Point Design implementation are highlighted and
explained in Specification Exceptions
Features
• Hardware and software register compatible with all
standard 16450 UARTs
• Implements all standard serial interface protocols
- 5, 6, 7, or 8 bits per character
- Odd, Even, or no parity detection and generation
- 1, 1.5, or 2 stop bit detection and generation
- Internal baud rate generator and separate receiver
clock input
- Modem control functions
- False start bit detection and recovery
- Prioritized transmit, receive, line status, and
modem control interrupts
- Line break detection and generation
- Internal loop back diagnostic functionality
• Registers
- Receiver Buffer Register (Read Only)
- Transmitter Holding Register (Write Only)
- Interrupt Enable Register
- Interrupt Identification Register (Read Only)
- Line Control and Line Status Registers
- Modem Control and Modem Status Registers
• Scratch Register
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Virtex-II Pro^™, Virtex^™,
Virtex-II^™, Virtex-4^™, QPro^™-R
Virtex-II, QPro Virtex-II, Virtex-E,
Spartan-II^™, Spartan-IIE^™,
Spartan-3^™
Version of Core
opb_uart16450
v1.00c
Resources Used
Min
Max
Slices
341
341
LUTs
357
357
FFs
347
347
Block RAMs
0
0
Provided with Core
Documentation
Product Specification.
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation
N/A
Template
Reference Designs
None
Design Tool Requirements
Xilinx Implementation
Tools
5.1i or later
Verification
N/A
Simulation
ModelSim SE/EE 5.6e or later
Synthesis
XST
Support
Support provided by Xilinx, Inc.
- Divisor Latch (least and more significant byte)
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS433 August 18, 2004
www.xilinx.com
1
Product Specification
1-800-255-7778