DS442 Datasheet, PDF (1/8 Pages) Xilinx, Inc – OPB to DCR Bridge

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OPB to DCR Bridge (v1.00b)
DS442 April 24, 2009
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Product Specification
Introduction
The OPB to DCR Bridge translates transactions
received on its OPB slave interface into DCR master
operations. Its design utilizes an Intellectual Property
Interface (IPIF) module to abstract OPB transactions
into a simple SRAM style protocol that is easier to
design with.
The device control register (DCR) bus is used primarily
for accessing the status and control registers within the
various OPB masters and slaves. The main advantage
of using the bridge, instead of the CPU to control the
DCR bus, is that it provides a memory mapped
interface that may be preferable to the use of special
move to/move from DCR instructions.
Because the bridge typically runs at a slower clock
frequency than the CPU, its timing requirements are
also less stringent. The OPB to DCR Bridge implements
a simple and flexible method for communicating with
DCR devices.
Features
• 32-bit DCR master with a 10-bit DCR address bus
• Memory-mapped interface from OPB to DCR, no
special instructions required
• Increased timing flexibility in typical systems where
the OPB clock is slower than the CPU clock
• Allows master devices other than the CPU to access
the DCR bus
• Provides a mechanism where CoreConnect systems
without a CPU can support DCR devices
LogiCORE™ IP Facts
Core Specifics
See EDK Supported Device Families.
Version of Core
opb to
dcr_bridge
v1.00b
Resources Used
Min
Max
Slices
LUTs
See Table 4 and Table 5
FFs
Block RAMs
N/A
N/A
Provided with Core
Documentation
Design Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs
None
Design Tool Requirements
Xilinx®
Implementation Tools
Verification
See Tools for requirements.
Simulation
Synthesis
Support
Provided by Xilinx, Inc.
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DS442 April 24, 2009
www.xilinx.com
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Product Specification