DS437 Datasheet, PDF (1/70 Pages) Xilinx, Inc – OPB PCI Full Bridge (v1.02a)

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OPB PCI Full Bridge (v1.02a)
DS437 January 25, 2006
00
Product Specification
Introduction
The OPB PCI Full Bridge design provides full bridge
functionality between the Xilinx 32-bit OPB and a 32-bit
Revision 2.2 compliant Peripheral Component
Interconnect (PCI) bus. The bridge is referred to as the
OPB PCI Bridge in this document.
The Xilinx OPB is a 32-bit bus subset of the IBM OPB
described in the 64-Bit On-Chip Peripheral Bus
Architecture Specification v2.0. Details on the Xilinx OPB,
the OPB IPIF, including DMA operation, is found in the
Processor IP Reference Guide. This guide is accessed via
EDK help or the Xilinx website at:
http://www.xilinx.com/ise/embedded/proc_ip_ref_
guide.pdf.
The LogiCORE PCI v3.0 core provides an interface with
the PCI bus. Details of the LogiCORE PCI 32 v3.0 core
operation is found in the Xilinx LogiCORE PCI Interface
v3.0 Product Specification and the Xilinx The Real-PCI
Design Guide v3.0.
Host bridge functionality (often called North bridge
functionality) is an optional functionality.
Configuration read and write PCI commands can be
performed from the OPB-side of the bridge. The OPB
PCI Bridge supports a 32-bit/33 MHz PCI bus only.
Exceptions to the support of PCI commands supported
by the v3.0 core are outlined in the Features section.
The OPB PCI Bridge design has parameters that allow
customers to configure the bridge to suit their
application. The parameterizable features of the design
are discussed in the Bus Interface Parameters section.
LogiCORE™ Facts
Core Specifics
Supported Device
Family
QPro™-R Virtex™-II, QPro
Virtex-II, Spartan™-II, Spartan-IIE,
Spartan-3 ⁽¹⁾, Virtex, Virtex-II,
Virtex-E, Virtex-II Pro, Virtex-4
Version of Core
opb_pci
v1.02a
Resources Used
Virtex-II
Min
Max
I/O (PCI)
47
50
I/O (OPB-related)
153
155
LUTs
415
4155
FFs
445
2105
Block RAMs
0
2 or more
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
example UCF-file
Verification
N/A
Instantiation Template
N/A
Reference Designs
None
Design Tool Requirements
Xilinx Implementation
Tools
8.1.1i or later
Verification
N/A
Simulation
ModelSim SE/EE 5.6e or later
Synthesis
XST
Support
Support provided by Xilinx, Inc.
Notes:
1. Available under Early Access condition only.
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and
registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application,
or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen-
tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple-
mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS437 January 25, 2006
www.xilinx.com
1
Product Specification