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DS416 Datasheet, PDF (1/50 Pages) Xilinx, Inc – Supports up to 2 physical channels
DS416 April 24, 2009
Direct Memory Access and
Scatter Gather (v2.01a)
Product Specification
Introduction
The DMA SG service is a continuation of the Xilinx
family of IBM CoreConnect compatible LogiCORE
products. It provides direct memory access (DMA)
allowing for a bounded number of sequential data
transfers to take place between regions in the address
space, typically between memory and an I/O device,
without processor management of individual transfers.
This service also provides Scatter Gather (SG) function-
ality allowing a sequence of DMA operations to be pre-
specified by software and performed automatically
without further processor intervention. The Xilinx
DMA SG is available for use as a service within the OPB
and PLB V3 Master with Local Link.
Features
• Available as a service in selected Master IPIFs
• Supports up to 2 physical channels
• Supports Split bus operation for simultaneous
independent Transmit and Receive DMA
operations
• Supports Simple DMA, Simple SG, and Packet SG
• Interrupt event reporting for each channel
• Supports optional Interrupt coalescing
• Supports user definable Local Link Headers and
Footers for use with functions such as checksum
off loading
• Supports Scatter Gather Buffer Descriptor
inserting and appending on active Buffer
Descriptor chains
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Virtex®-4
Version of Core
dma_sg
v2.01a
Resources Used
Min
Max
Slices
185
1089
LUTs
176
1296
FFs
216
1160
Block RAMs
0
1
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
None
Verification
EDK Simulation Support
Instantiation Template
Wizard Support
Design Tool Requirements
Xilinx Implementation
Tools
Xilinx EDK 1.1
Verification
Mentor Graphics ® ModelSim®
6.4be or later
Simulation
ModelSim 6.4bor later
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other countries. All other trademarks are the property of their respective owners.
DS416 April 24, 2009
www.xilinx.com
1
Product Specification