DS403 Datasheet, PDF (1/11 Pages) Xilinx, Inc – Supports low latency point-to-point topology

DS403 December 13, 2007
0
PLBV46 to OPB Bridge
(v1.00a)
00
Product Specification
Introduction
The Processor Local Bus Version 4.6 (PLBV46) to
On-chip Peripheral Bus (OPBv20) Bridge translates
PLBv46 transactions into OPB transactions. The system
designer uses the bridge in systems where a PLBv46
master device requires access to legacy OPB
peripherals.
Features
• Bridges transactions as a 32-bit PLBv46 slave and
32-bit OPBv20 master.
• PLBv46 Slave interface
- Supports connections to a 32-, 64-, or 128-bit
PLBv46 bus and transactions from 32-, 64- and
128-bit masters that can talk to 32-bit slaves.
- Decodes up to four separate address ranges with
programmable lower and upper address
boundaries for each range
- Single transfers of 1-4 bytes. Read data mirroring
supports conversion cycles from larger masters.
- Supports only fixed length, burst transactions of
up to sixteen quad-words, double-words, words,
(for appropriately sized masters.)
- Cacheline transactions of 4 and 8 words
- Supports up to 8 PLBv46 masters (number of
PLBv46 masters configurable via a design
parameter)
- Supports low latency point-to-point topology
- 16-word buffer to increase PLBv46 bus utilization
via posted writes.
• OPB Master interface
- Utilizes byte enable interface
- The OPB master re-attempts all slave retried
transactions until they complete
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Spartan^™ 3, Virtex™-II Pro,
Virtex-4, Virtex-5,
Version of Core
plbv46_opb_
bridge
v1_00_a
Resources Used
Min
Max
Slices
180
199
LUTs
285
312
FFs
188
244
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs
None
Design Tool Requirements
Xilinx Implementation
Tools
9.1i or later
Verification
N/A
Simulation
ModelSim SE/EE 6.1e or later
Synthesis
XST
Support
Support provided by Xilinx, Inc.
© 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective
owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx
makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly
disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims
of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS403 December 13, 2007
www.xilinx.com
1
Product Specification