DS402 Datasheet, PDF (1/9 Pages) Xilinx, Inc – Daisy-chain connections for the DCR data bus

DS402 April 19, 2010
LogiCORE IP Device Control
Register Bus (DCR) v2.9 (v1.00b)
Product Specification
Introduction
The Xilinx 32-Bit Device Control Register Bus (DCR), a
soft IP core designed for Xilinx FPGAs, provides the
DCR bus structure as described in the IBM 32-Bit Device
Control Register Bus (DCR) Architecture Specification to
allow easy connection of the DCR Master to the DCR
slaves. It provides the daisy-chain for the DCR data bus
and the OR gate for the DCR acknowledge signals from
the DCR slaves.
Features
• DCR connections for one DCR master and a
variable number of DCR slaves, which are
configurable via design parameter
• Daisy-chain connections for the DCR data bus
• Required OR function of the DCR slaves’
acknowledge signal
LogiCORE™ IP Facts
Supported Device
Family ⁽¹⁾
Core Specifics
Virtex^®-5/-5FX, Virtex-4/-4Q/-4QV,
Automotive Spartan^®-3/-3E/-3A,
-3A DSP
Resources Used
See Table 4 & Table 5.
Special Features
None
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Additional Items
None
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 12.1
Verification
Mentor Graphics ModelSim
v6.5c and above
Simulation
Mentor Graphics ModelSim
v6.5c and above
Synthesis
XST
Support
Provided by Xilinx, Inc.
1. For a complete list of supported devices, see the 12.1
release notes for this core.
© 2002-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS402 April 19, 2010
www.xilinx.com
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Product Specification